Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

A New Process and Framework for Direct Anonymous Attestation Based on Asymmetric Bilinear Maps

For the problem of security properties scale badly of the Direct anonymous attestation （DAA） scheme based symmetric bilinear pairing, a new DAA scheme based on asymmetric bilinear pairing, which gives a new practical solution to ECC-based TPM in protecting the privacy of TPM,is presented. The scheme takes on new process and framework in sign protocol, of which the TPM has only to perform three exponentiations, moreover, the signature which isn＇t knowledge of signature, is a signature of the ordinary ecliptic curve system itself. Compared to other schemes, the whole performance of the scheme is the best,and the scheme not only satisfies the same proper- ties, but also is more simple and efficient. This paper gives not only a detailed security proof of the proposed scheme which shows that the scheme meets the security require- ments of anonymity and unlinkability,but also a careful performance analysis by comparing with the existing DAA schemes.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

太阳跟踪自动化控制系统设计

随着太阳能不断被人类发现利用,如何应用自动控制系统有效捕捉太阳能更是当前自动化业界所面临的最新课题,本次设计就是利用自动控制技术实现了对太阳能的最大化合理应用。本系统阐述了自动化控制系统的设计过程以及软硬件部分的设计,系统采用AT89S52单片机作为整个系统的控制核心,系统采用了两种追踪模式：光电检测追踪模式和太阳角度追踪模式。晴天时系统采用光电检测追踪模式,而阴天时系统进入太阳角度追踪模式。在光电检测追踪模式下,光电检测部分采用光电二极管作为光电传感器,利用硬件装置通过光电二极管的比较电路来判断太阳的方位,从而达到了追踪太阳的目的。在太阳角度追踪模式下,要是通过软件计算当时当地太阳高度角和太阳方位角,再配合硬件来实现对太阳的追踪。系统的软件和硬件采用模块化设计思想,完成了系统的制作。     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

用于流水线ADC的频率自适应可编程MDAC电路

A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.     

Software-Defined Data Center

Defining a software-defined data center is a vision of the future.An SDDC brings together software-defined compute,software-de fined network,software-defined storage,software-defined hypervisor,software-defined availability,and software-defined security.It also unifies the control planes of each individual software-defined component.A unified control plane enables rich resource abstrac tions for purpose-fit orchestration systems and/or programmable infrastructures.This enables dynamic optimization according to busi ness requirements.     

具有缓冲层和N型埋层的高压兼容Bi-CMOS工艺的超结LDMOS

A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.     

纳米锥SiGe-SOI光波导与光纤的耦合分析

Based on a submicrometer-sized SiGe-SOI waveguide, the coupling loss mechanism is analyzed between the submicrometer-sized SiGe-SOI waveguide and the fiber. The main sources of coupling loss are analyzed, and the mismatch loss of the mode field is the mainly lost during connection between the submicrometer-sized waveguide and the fiber. In order to reduce the mismatch loss of the mode field, the structure ofa nanotaper SiGeSOI waveguide with a nanometer-sized tip is adopted. By reducing the waveguide dimensions to increase the mode field size, coupling loss could be reduced between the waveguide and the fiber. Different mode field dimensions ofnanotaper SiGe-SOI waveguides and fiber are quantitatively analyzed, and the quantitative relationship between nanotaper SiGe-SOI waveguide dimensions and mode field dimensions are obtained. Finally, nanotaper SiGe-SOI waveguides are made, and the test and analysis have been done. The final experimental results accord well with the theoretical analysis. When the waveguide width is 0.5 μm, the minimum coupling loss of the SiGe-SOI waveguide is 0.56 dB/facet, and also the correctness of the design method and theoretical analysis are verified.     

多层铜布线CMP后表面残留CuO颗粒的去除研究

This article introduces the removal technology of CuO particles on the post CMP wafer surface of multi-layered copper. According to the Cu film corrosion curve with different concentrations of HEO2 and the effect curve of time on the growth rate of CuO film, CuO film with the thickness of 220 nm grown on Cu a surface was successfully prepared without the interference of CuC12.2H20. Using the static corrosion experiment the type of chelating agent （FA/O II type chelating agent） and the concentration range （10-100 ppm） for CuO removal was determined, and the Cu removal rate was close to zero. The effect of surfactant on the cleaning solution properties was studied, and results indicated that the surfactant has the effect of reducing the surface tension and viscosity of the cleaning solution, and making the cleaning agent more stable. The influence of different concentrations of FA/O I type surfactant and the mixing of FA/O II type chelating agent and FA/O I type surfactant on the CuO removal effect and the film surface state was analyzed. The experimental results indicated that when the concentration of FA/O I type surfactant was 50 ppm, CuO particles were quickly removed, and the surface state was obviously improved. The best removal effect of CuO on the copper wiring film surface was achieved with the cleaning agent ratio of FA/O II type chelating agent 75 ppm and FA/O I type surfactant 50 ppm. Finally, the organic residue on the copper pattern film after cleaning with that cleaning agent was detected, and the results showed that the cleaning used agent did not generate organic residues on the film surface, and effectively removes the organic residue on the water.     

Continuous Clustering Trajectory Stream of Moving Objects

The clustering of trajectories over huge volumes of streaming data has been rec- ognized as critical for many modem applica- tions. In this work, we propose a continuous clustering of trajectories of moving objects over high speed data streams, which updates online trajectory clusters on basis of incremental line- segment clustering. The proposed clustering algorithm obtains trajectory clusters efficiently and stores all closed trajectory clusters in a bi- tree index with efficient search capability. Next, we present two query processing methods by utilising three proposed pruning strategies to fast handle two continuous spatio-temporal queries, threshold-based trajectory clustering queries and threshold-based trajectory outlier detections. Finally, the comprehensive experi- mental studies demonstrate that our algorithm achieves excellent effectiveness and high effi- ciency for continuous clustering on both syn- thetic and real streaming data, and the propo- sed query processing methods utilise average 90% less time than the naive query methods.     

基于一种新架构的4GH 32比特的直接数字频率合成器

This paper presents a novel direct digital frequency synthesizer(DDFS)architecture based on nonlinear DAC coarse quantization and the ROM-based piecewise approximation method,which has the advantages of high speed,low power and low hardware resources.By subdividing the sinusoid into a collection of phase segments,the same initial value of each segment is realized by a nonlinear DAC.The ROM is decomposed with a coarse ROM and fine ROM using the piecewise approximation method.Then,the coarse ROM stores the offsets between the initial value of the common segment and the initial value of each line in the same segment.Meanwhile,the fine ROM stores the differences between the line values and the initial value of each line.A ROM compression ratio of32 can be achieved in the case of 11 bit phase and 9 bit amplitude.Based on the above method,a prototype chip was fabricated using 1.4 m GaAs HBT technology.The measurement shows an average spurious-free dynamic range(SFDR)of 45 dBc,with the worst SFDR only 40.07 dBc at a 4.0 GHz clock.The chip area is 4.6 3.7 mm2and it consumes 7 W from a–4.9 V power supply.     

A novel SOI high-voltage SJ-pLDMOS based on self-adaptive charge balance

A new SOl self-balance （SB） super-junction （S J） pLDMOS with a self-adaptive charge （SAC） layer and its physical model are presented. The SB is an effective way to realize charges balance （CB）. The substrate-assisted depletion （SAD） effect of the lateral SJ is eliminated by the self-adaptive inversion electrons provided by the SAC. At the same time, high concentration dynamic self-adaptive electrons effectively enhance the electric field （EI） of the dielectric buried layer and increase breakdown voltage （BV）. E1 = 600 V/μm and BV =- 237 V are obtained by 3D simulation on a 0.375-μm-thick dielectric layer and a 2.5-μm-thick top silicon layer. The optimized structure realizes the specific on resistance （Ron,sp） of 0.01319Ω·cm2, FOM （FOM = BV2/R p） of 4.26 MW/cm2 under a 11 μm length （Ld） drift region.