Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors

Transparent electronic devices formed on flexible substrates are expected to meet emerging technological demands where silicon-based electronics cannot provide a solution. Examples of active flexible applications include paper displays and wearable computers. So far, mainly flexible devices based on hydrogenated amorphous silicon (a-Si:H) and organic semiconductors have been investigated. However, the performance of these devices has been insufficient for use as transistors in practical computers and current-driven organic light-emitting diode displays. Fabricating high-performance devices is challenging, owing to a trade-off between processing temperature and device performance. Here, we propose to solve this problem by using a novel semiconducting material--namely, a transparent amorphous oxide semiconductor from the In-Ga-Zn-O system (a-IGZO)--for the active channel in transparent thin-film transistors (TTFTs). The a-IGZO is deposited on polyethylene terephthalate at room temperature and exhibits Hall effect mobilities exceeding 10 cm2 V(-1) s(-1), which is an order of magnitude larger than for hydrogenated amorphous silicon. TTFTs fabricated on polyethylene terephthalate sheets exhibit saturation mobilities of 6-9 cm2 V(-1) s(-1), and device characteristics are stable during repetitive bending of the TTFT sheet.     

Patterning organic single-crystal transistor arrays

Field-effect transistors made of organic single crystals are ideal for studying the charge transport characteristics of organic semiconductor materials. Their outstanding device performance, relative to that of transistors made of organic thin films, makes them also attractive candidates for electronic applications such as active matrix displays and sensor arrays. These applications require minimal cross-talk between neighbouring devices. In the case of thin film systems, simple patterning of the active semiconductor layer minimizes cross-talk. But when using organic single crystals, the only approach currently available for creating arrays of separate devices is manual selection and placing of individual crystals-a process prohibitive for producing devices at high density and with reasonable throughput. In contrast, inorganic crystals have been grown in extended arrays, and efficient and large-area fabrication of silicon crystalline islands with high mobilities for electronic applications has been reported. Here we describe a method for effectively fabricating large arrays of single crystals of a wide range of organic semiconductor materials directly onto transistor source-drain electrodes. We find that film domains of octadecyltriethoxysilane microcontact-printed onto either clean Si/SiO(2) surfaces or flexible plastic provide control over the nucleation of vapour-grown organic single crystals. This allows us to fabricate large arrays of high-performance organic single-crystal field-effect transistors with mobilities as high as 2.4 cm(2) V(-1) s(-1) and on/off ratios greater than 10(7), and devices on flexible substrates that retain their performance after significant bending. These results suggest that our fabrication approach constitutes a promising step that might ultimately allow us to utilize high-performance organic single-crystal field-effect transistors for large-area electronics applications.     

High-mobility ultrathin semiconducting films prepared by spin coating

The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (approximately 50 A), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS(2-x)Se(x) films, which exhibit n-type transport, large current densities (>10(5) A cm(-2)) and mobilities greater than 10 cm2 V(-1) s(-1)--an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).     

Tuning charge transport in solution-sheared organic semiconductors using lattice strain

Circuits based on organic semiconductors are being actively explored for flexible, transparent and low-cost electronic applications. But to realize such applications, the charge carrier mobilities of solution-processed organic semiconductors must be improved. For inorganic semiconductors, a general method of increasing charge carrier mobility is to introduce strain within the crystal lattice. Here we describe a solution-processing technique for organic semiconductors in which lattice strain is used to increase charge carrier mobilities by introducing greater electron orbital overlap between the component molecules. For organic semiconductors, the spacing between cofacially stacked, conjugated backbones (the π-π stacking distance) greatly influences electron orbital overlap and therefore mobility. Using our method to incrementally introduce lattice strain, we alter the π-π stacking distance of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) from 3.33?? to 3.08??. We believe that 3.08?? is the shortest π-π stacking distance that has been achieved in an organic semiconductor crystal lattice (although a π-π distance of 3.04?? has been achieved through intramolecular bonding). The positive charge carrier (hole) mobility in TIPS-pentacene transistors increased from 0.8?cm(2)?V(-1)?s(-1) for unstrained films to a high mobility of 4.6?cm(2)?V(-1)?s(-1) for a strained film. Using solution processing to modify molecular packing through lattice strain should aid the development of high-performance, low-cost organic semiconducting devices.     

Inkjet printing of single-crystal films

The use of single crystals has been fundamental to the development of semiconductor microelectronics and solid-state science. Whether based on inorganic or organic materials, the devices that show the highest performance rely on single-crystal interfaces, with their nearly perfect translational symmetry and exceptionally high chemical purity. Attention has recently been focused on developing simple ways of producing electronic devices by means of printing technologies. 'Printed electronics' is being explored for the manufacture of large-area and flexible electronic devices by the patterned application of functional inks containing soluble or dispersed semiconducting materials. However, because of the strong self-organizing tendency of the deposited materials, the production of semiconducting thin films of high crystallinity (indispensable for realizing high carrier mobility) may be incompatible with conventional printing processes. Here we develop a method that combines the technique of antisolvent crystallization with inkjet printing to produce organic semiconducting thin films of high crystallinity. Specifically, we show that mixing fine droplets of an antisolvent and a solution of an active semiconducting component within a confined area on an amorphous substrate can trigger the controlled formation of exceptionally uniform single-crystal or polycrystalline thin films that grow at the liquid-air interfaces. Using this approach, we have printed single crystals of the organic semiconductor 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C(8)-BTBT) (ref. 15), yielding thin-film transistors with average carrier mobilities as high as 16.4?cm(2)?V(-1)?s(-1). This printing technique constitutes a major step towards the use of high-performance single-crystal semiconductor devices for large-area and flexible electronics applications.     

Flexible metal-oxide devices made by room-temperature photochemical activation of sol-gel films

Amorphous metal-oxide semiconductors have emerged as potential replacements for organic and silicon materials in thin-film electronics. The high carrier mobility in the amorphous state, and excellent large-area uniformity, have extended their applications to active-matrix electronics, including displays, sensor arrays and X-ray detectors. Moreover, their solution processability and optical transparency have opened new horizons for low-cost printable and transparent electronics on plastic substrates. But metal-oxide formation by the sol-gel route requires an annealing step at relatively high temperature, which has prevented the incorporation of these materials with the polymer substrates used in high-performance flexible electronics. Here we report a general method for forming high-performance and operationally stable metal-oxide semiconductors at room temperature, by deep-ultraviolet photochemical activation of sol-gel films. Deep-ultraviolet irradiation induces efficient condensation and densification of oxide semiconducting films by photochemical activation at low temperature. This photochemical activation is applicable to numerous metal-oxide semiconductors, and the performance (in terms of transistor mobility and operational stability) of thin-film transistors fabricated by this route compares favourably with that of thin-film transistors based on thermally annealed materials. The field-effect mobilities of the photo-activated metal-oxide semiconductors are as high as 14 and 7?cm(2)?V(-1)?s(-1) (with an Al(2)O(3) gate insulator) on glass and polymer substrates, respectively; and seven-stage ring oscillators fabricated on polymer substrates operate with an oscillation frequency of more than 340?kHz, corresponding to a propagation delay of less than 210?nanoseconds per stage.     

Low-voltage organic transistors with an amorphous molecular gate dielectric

Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick gate dielectric layers: these dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in dielectric thickness leads to ever greater gate leakage and power dissipation.     

Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates

The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of application in consumer and other areas of electronics.     

General observation of n-type field-effect behaviour in organic semiconductors

Organic semiconductors have been the subject of active research for over a decade now, with applications emerging in light-emitting displays and printable electronic circuits. One characteristic feature of these materials is the strong trapping of electrons but not holes: organic field-effect transistors (FETs) typically show p-type, but not n-type, conduction even with the appropriate low-work-function electrodes, except for a few special high-electron-affinity or low-bandgap organic semiconductors. Here we demonstrate that the use of an appropriate hydroxyl-free gate dielectric--such as a divinyltetramethylsiloxane-bis(benzocyclobutene) derivative (BCB; ref. 6)--can yield n-channel FET conduction in most conjugated polymers. The FET electron mobilities thus obtained reveal that electrons are considerably more mobile in these materials than previously thought. Electron mobilities of the order of 10(-3) to 10(-2) cm(2) V(-1) s(-1) have been measured in a number of polyfluorene copolymers and in a dialkyl-substituted poly(p-phenylenevinylene), all in the unaligned state. We further show that the reason why n-type behaviour has previously been so elusive is the trapping of electrons at the semiconductor-dielectric interface by hydroxyl groups, present in the form of silanols in the case of the commonly used SiO2 dielectric. These findings should therefore open up new opportunities for organic complementary metal-oxide semiconductor (CMOS) circuits, in which both p-type and n-type behaviours are harnessed.     

铋掺杂氧化铟锌薄膜晶体管的研究

采用射频磁控溅射法制备了以非晶铋掺杂氧化铟锌(a-IZBO)为沟道层的薄膜晶体管(TFTs).相比本征的氧化铟锌薄膜晶体管,a-IZBO-TFTs显示出更低的关态电流,正向偏移的开启电压,表明铋掺杂能有效抑制载流子浓度.在铋掺杂含量为原子百分比8.6%时达到最佳的电学性能:载流子迁移率为7.5cm~2/(V·s),开关比为3×10~8,亚阈值摆幅为0.41V/decade.使用光致发光激发谱和X射线光电子能谱评价了a-IZBO沟道层中的氧空位缺陷,分析结果证实了铋的掺杂确实有效地减少了氧空位,从而抑制了半导体沟道层中的载流子浓度,对a-IZO-TFTs的总体电学性能改善起到较大的作用.     

低电压并五苯薄膜场效应晶体管

利用全蒸镀法, 以并五苯作为有源层, 聚甲基丙烯酸甲 酯（PMMA）作为绝缘层, 制备了全有机薄膜场效应晶体管（TFT）. 测试结果表明, 器件具有较低的工作电压和较高的场效应迁移率. 对工作机理进行了探讨.     

一种优越的钝化膜(a-Si:O:H)

本文报道了用等离子放电SiH_4+H_2+H_2O混合气体淀积氢化非晶硅氧合金膜,均匀、致密、耐腐蚀、半绝缘、电中性、富含氢,是较理想的半导体器件钝化膜。兼有SiO_2和a-Si:H的优点,而又克服了它们各自的缺点。用它钝化的平面晶体管放在盐水里几小时后,特性不变。     

Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures

Substantial effort has been placed on developing semiconducting carbon nanotubes and nanowires as building blocks for electronic devices--such as field-effect transistors--that could replace conventional silicon transistors in hybrid electronics or lead to stand-alone nanosystems. Attaching electric contacts to individual devices is a first step towards integration, and this step has been addressed using lithographically defined metal electrodes. Yet, these metal contacts define a size scale that is much larger than the nanometre-scale building blocks, thus limiting many potential advantages. Here we report an integrated contact and interconnection solution that overcomes this size constraint through selective transformation of silicon nanowires into metallic nickel silicide (NiSi) nanowires. Electrical measurements show that the single crystal nickel silicide nanowires have ideal resistivities of about 10 microOmega cm and remarkably high failure-current densities, >10(8) A cm(-2). In addition, we demonstrate the fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal-semiconductor interfaces. We produce field-effect transistors based on those heterostructures in which the source-drain contacts are defined by the metallic NiSi nanowire regions. Our approach is fully compatible with conventional planar silicon electronics and extendable to the 10-nm scale using a crossed-nanowire architecture.     

量子化学研究不同取代基对六苯并蔻电荷传输性能的影响

应用密度泛函理论在B3LYP/6-311+G(d)、M06-2X/6-311+G(d)、CAM-B3LYP/6-311+G(d)理论水平,分别计算12个不同取代基取代的六苯并蔻分子的电荷传输速率.研究结果显示，采用长程较正泛函CAMB3LYP更适合目标体系的电荷传输性能研究.在六苯并蔻环上，引入6个—CH₃与—CN取代基，得到的六苯并蔻衍生物分子与母体六苯并蔻相比，空穴迁移率相对较大，分别为2.51、0.92 cm²·V^-1·s^-1，可设计为性能优良的p型有机半导体分子；引入6个—SH、—CH2SCH₃及—COOCH₃取代基，得到的3个分子与母体六苯并蔻相比，对分子的电荷传输速率改善较小；引入—SCH₃、—OCH₃、—OH、—NHCH₃、—N(CH₃)2等5个取代基，所得到的5个分子电子迁移速率为空穴迁移速率的1.7～18倍，有望设计成性能优良的n型有机半导体材料.     

a-St:H FET特性的研究

本文从理论和实验两方面对a-Si:H FET的特性进行分析研究。给出了一种关于a-Si:H FET新的理论分析方法,假设a-Si:H能隙中深局域态密度和带尾局域态密度均为指数分布,并且考虑到漏源电压对沟道表面势的影响,采用简便的方法和合理的近似推导出了较全面反映a-Si:H FET特性的解析表达式。同时在实验中,研制了用SiO_2或Si_3N_4作为栅绝缘层的a-Si:H FET,测量得到了不同绝缘层和不同沟道长度的各a-Si:H FET的直流特性。当栅压变化20V时,漏源电流可以变化10~4。最后,对理论计算及实验结果进行了分析和比较。     

退火温度对ZnO薄膜晶体管电特性的影响

针对非晶硅和有机薄膜晶体管的低迁移率问题,以高纯Zn为靶材,反应磁控溅射沉积、且在不同温度下退火的ZnO薄膜作为半导体活性层,成功地制备出基于ZnO材料的薄膜晶体管(ZnO-TFT),研究了退火温度对ZnO -TFT电特性的影响.结果表明:ZnO- TFT的载流子迁移率随退火温度的升高而明显增大,700℃退火的样品迁移...     

Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors

Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied: such devices combine the high mobility of III-V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored-but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO(2) substrates. As a parallel with silicon-on-insulator (SOI) technology, we use 'XOI' to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO(x) layer (~1?nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6?mS?μm(-1) at a drain-source voltage of 0.5?V, with an on/off current ratio of greater than 10,000.     

纳米晶硅的光电特性

利用ＰＥＣＶＤ方法及后处理工艺制备了具有室温可见光区光致发光效应的纳米晶硅（ｎ－Ｓｉ／ＳｉＯ２）薄膜材料，对其光吸收，光能隙以及电导率等特性参数进行了测试研究。发现该薄膜的可见光区吸收比ＰＥＣＶＥ方法制备的微晶硅，非晶硅等薄膜的光吸收明显减弱，且光能隙增大。而电导率则大大提高，达到１０－１－１０－３ｃｍ－１Ω－１的量级。该材料光学性能的变化可用量子尺寸效应进行定性解释，但其电导率的大幅度增加还有待进一步的研究。     

束参数对离子束溅射法所淀积非晶硅电特性的影响

本文论述了用离子束溅射淀积非晶硅(a-Si)和氢化非晶硅(a-Si:H)的方法,提供了加速电压和衬底位置改变对薄膜暗电阻率的影响结果,通过有关淀积工艺条件的研究,得出了一些有用的结论。     

High-performance thin-film transistors using semiconductor nanowires and nanoribbons

Thin-film transistors (TFTs) are the fundamental building blocks for the rapidly growing field of macroelectronics. The use of plastic substrates is also increasing in importance owing to their light weight, flexibility, shock resistance and low cost. Current polycrystalline-Si TFT technology is difficult to implement on plastics because of the high process temperatures required. Amorphous-Si and organic semiconductor TFTs, which can be processed at lower temperatures, but are limited by poor carrier mobility. As a result, applications that require even modest computation, control or communication functions on plastics cannot be addressed by existing TFT technology. Alternative semiconductor materials that could form TFTs with performance comparable to or better than polycrystalline or single-crystal Si, and which can be processed at low temperatures over large-area plastic substrates, should not only improve the existing technologies, but also enable new applications in flexible, wearable and disposable electronics. Here we report the fabrication of TFTs using oriented Si nanowire thin films or CdS nanoribbons as semiconducting channels. We show that high-performance TFTs can be produced on various substrates, including plastics, using a low-temperature assembly process. Our approach is general to a broad range of materials including high-mobility materials (such as InAs or InP).