YON界面钝化层改善HfO2/Ge界面特性的研究

本文采用YON界面钝化层来改善HfO₂栅介质Ge metal-oxide-semiconductor（MOS）器件的界面质量和电特性.比较研究了两种不同的YON制备方法：在Ar+N₂氛围中溅射Y₂O₃靶直接淀积获得以及先在Ar+N₂氛围中溅射Y靶淀积YN再于含氧氛围中退火形成YON.实验结果及XPS的分析表明,后者可以利用YN在退火过程中先于Ge表面吸收从界面扩散的O而氧化,从而阻挡了O扩散到达Ge表面,更有效抑制了界面处Ge氧化物的形成,获得了更优良的界面特性和电特性：较小的CET（1.66 nm）,较大的k值（18.8）,较低的界面态密度（7.79×10¹¹ eV^-1cm^-2）和等效氧化物电荷密度（-4.83×10¹² cm^-2）,低的栅极漏电流（3.40×10^-4 A/cm²@V_g=V_fb+1 V）以及好的高场应力可靠性.     

InAs/GaSb Ⅱ类超晶格长波红外探测器的表面处理研究

开展了In As/Ga Sb Ⅱ类超晶格长波红外探测器的表面处理研究。通过对不同处理工艺形成台面器件的暗电流分析,发现N₂O等离子处理结合快速热退火(RTA)的优化工艺能够显著改善长波器件电学性能。对于50%截止波长12.3μm的长波器件,在液氮温度,-0.05 V偏置下,表面处理后暗电流密度从5.88×10^-1 A/cm²降低至4.09×10^-2 A/cm²,零偏下表面电阻率从17.7Ωcm提高至284.4Ωcm,有效降低侧壁漏电流。但是该表面处理后的器件在大反偏压下仍有较大的侧壁漏电,这可能是由于高浓度的表面电荷使得大反偏下侧壁存在较高的隧穿电流。通过栅控结构器件的变栅压实验,验证了长波器件存在纯并联电阻及表面隧穿两种主要漏电机制。最后,对表面处理前后的暗电流进行拟合,处理后器件表面电荷浓度为3.72×10¹¹ cm^-2。     

高k栅介质增强型β-Ga2O3 VDMOS器件的单粒子栅穿效应研究

以增强型β-Ga₂O₃ VDMOS器件作为研究对象,利用TCAD选择不同的栅介质材料作为研究变量,观察不同器件的单粒子栅穿效应敏感性。高k介质材料Al₂O₃和HfO₂栅介质器件在源漏电压200 V、栅源电压-10 V的偏置条件下能有效抵御线性能量转移为98 MeV·cm²/mg的重离子攻击,SiO₂栅介质器件则发生了单粒子栅穿效应(Single event gate rupture, SEGR)。采用HfO₂作为栅介质时源漏电流和栅源电流分别下降92%和94%,峰值电场从1.5×10⁷ V/cm下降至2×10⁵ V/cm,避免了SEGR的发生。SEGR发生的原因是沟道处累积了大量的空穴,栅介质中的临界电场超过临界值导致了击穿,而高k栅介质可以有效降低器件敏感区域的碰撞发生率,抑制器件内电子空穴对的进一步生成,降低空穴累积的概率。     

4H-SiC TSOB结势垒肖特基二极管静态特性

为增强器件的反向耐压能力,降低器件的漏电功耗,采用Silvaco TCAD对沟槽底部具有SiO₂间隔的结势垒肖特基二极管(TSOB)的器件特性进行了仿真研究。通过优化参数来改善导通压降(V_F)-反向漏电流(I_R)和击穿电压的折衷关系。室温下,沟槽深度为2.2 μm时,器件的击穿电压达到1 610 V。正向导通压降为2.1 V,在V_F=3 V时正向电流密度为199 A/cm²。为进一步改善器件的反向阻断特性,在P型多晶硅掺杂的有源区生成一层SiO₂来优化漂移区电场分布,此时改善的器件结构在维持正向导通压降2.1 V的前提下,击穿电压达到1 821 V,增加了13%。在1 000 V反向偏置电压下,反向漏电流密度比普通结构降低了87%,有效降低了器件的漏电功耗。普通器件结构的开/关电流比为2.6×10³(1 V/-500 V),而改善的结构为1.3×10⁴(1 V/-500 V)。     

接触面陷阱密度对a-InSnZnO薄膜晶体管器件电气性能的影响研究

We reported the influence of interface trap density（Nt） on the electrical properties of amorphous InSnZnO based thin-film transistors,which were fabricated at different direct-current（DC） magnetron sputtering powers.The device with the smallest N_t of 5.68×10¹¹ cm^-2 and low resistivity of 1.21×10^-3Ω·cm exhibited a turn-on voltage(V_ON) of-3.60 V,a sub-threshold swing（S.S） of 0.16 V/dec and an on-off ratio(I_ON/I_OFF) of⁸ x 108.With increasing N_t,the V_ON,S.S and I_ON/I_OFF were suppressed to-9.40 V,0.24 V/dec and 2.59×10⁸,respectively.The V_TH shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices.The result showed that the reduction in N_t contributes to an improvement in the electrical properties and stability.     

仿真研究下一代钙钛矿基辐照探测器

近年来,金属卤化物钙钛矿材料因其强大的X射线吸收能力、高灵敏度和低制备成本而受到广泛关注^[1]。本文基于二维漂移-扩散方程,模拟了铯银铋溴(Cs₂AgBiBr₆)钙钛矿基探测器的辐照响应特性。根据仿真结果显示,钙钛矿(Cs₂AgBiBr₆)基、硅(Si)基和非晶硒(α-Se)基的探测器之光电流依次可达8.1×10^-3、1.1×10^-3和5.7×10^-5A。此外,钙钛矿基和非晶硒基探测器的光暗电流比(PDR)分别为9759和140000,远高于硅器件的水平。综合考虑成本及器件性能,Cs₂AgBiBr₆钙钛矿是有竞争力的新型辐照探测器有源层材料。     

基于穿通晶体管的低功耗离散工作模式

This paper proposed a discrete operation mode for a punchthrough（PT） phototransistor,which is suitable for low power application,since the bias current is only necessary during the read-out phase.Moreover,simulation results show that with the new operation mode,the photocurrent is much larger than that of continuous operation mode.An ultra-high responsivity of 2×10⁷A/W at 10^-9 W/cm² is obtained with a small detector size of 1μm².In CMOS image sensor applications,with an integration time of 10 ms,a normalized pixel responsivity of 220 V·m²/W·s·μm² is obtained without any auxiliary amplifier.     

重掺杂p型SiC晶片Ni/Al欧姆接触特性

系统研究了Al和Ni/Al两种金属体系在重掺杂p型SiC晶片上的欧姆接触特性和电学性质。利用X射线衍射、扫描电子显微镜和综合物性测量系统对这两种电极表面的微观结构和样品的电学性质进行了表征。结果表明：在真空环境下经过800℃退火后Al电极可呈现出欧姆接触行为,其比接触电阻率为1.98×10^-3Ω·cm²,退火处理后Al电极与SiC在接触界面形成化合物Al₄C₃,有助于提高接触界面稳定性。在Ni/Al复合体系中,当Ni金属层厚度为50 nm时,其比接触电阻率显著降低至4.013×10^-4Ω·cm²。退火后Ni与SiC在接触界面生成的Ni₂Si有利于欧姆接触的形成和降低比接触电阻率。研究结果可为开发液相法生长的p型SiC晶片电子器件提供参考。     

基于低温氧化的4H-SiC/SiO2界面态钝化方案

阐述4H-SiC晶圆的Si面上通过CVD淀积与低温热氧化生长的双层栅氧化物结构，在高温氮气环境下可降低4H-SiC/SiO₂界面的高密度界面缺陷。采用PECVD淀积一层均匀的SiO₂膜后，通过热氧化工艺在淀积膜与4H-SiC/SiO₂间生长一层很薄的氧化物过渡层。根据不同温区间热氧化温度形成的SiO₂膜晶型不同，改变界面中氮气退火过程中氮元素的引入，从而钝化4H-SiC/SiO₂的界面缺陷。     

界面陷阱分布对SiC MOSFET准静态C-V特性的影响

为了分析4H-SiC/SiO₂固定电荷和界面陷阱对MOSFET准静态电容-电压(C-V)特性曲线的影响机制，对不同栅氧氮退火条件下的n沟道4H-SiC双注入MOSFET(DIMOSFET)进行了氧化层中可动离子、界面陷阱分布和准静态C-V特性曲线的测试，并结合仿真探讨了测试频率、固定电荷、4H-SiC/SiO₂界面陷阱分布对准静态C-V特性曲线的影响。实验和仿真结果表明：电子和空穴界面陷阱分别影响准静态C-V曲线的右半部分和左半部分；界面陷阱的E₀、E_s、N₀(E₀为陷阱能级中心与导带底能级或价带顶能级之差，E_s为陷阱能级分布的宽度，N₀为陷阱能级分布的密度峰值)对准静态C-V曲线的影响是综合的；当E₀为0 eV,E_s为0.2 eV,电子和空穴捕获截面均为1×10^-18 cm²,电子和空穴界面陷阱的N₀分...     

Fabrication and characterization of metal-oxide-semiconductorfield-effect transistors and gated diodes using Ta2O5 gate oxide

N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta₂O₅, gate oxide were fabricated. The Ta₂O₅ films were deposited by plasma enhanced chemical vapor deposition. The I_DS-V_DS and I_DS-V_GS characteristics mere measured. The electron mobility was 333 cm²/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10¹² cm^-2 eV^-1, 780 cm/s and 3×10^-6 sec, respectively. A comparison with conventional MOSFETs using SiO₂ gate oxide was made     

Sulfide treated GaAs MISFET's with gate insulator of photo-CVDgrown P3N5 film

Sulfide passivated GaAs MISFET's with the gate insulator of photo-CVD grown P₃N₅ films have been successfully fabricated. The device shows the drain current instability less than 22% for the period of 1.0 s ~1.0×10⁴ s, due to excellent properties of sulfide treated P₃N₅/GaAs interface. The effective electron mobility and extrinsic transconductance of the device are about 1300 cm²/V·sec and 1.33 mS, respectively, at room temperature. To estimate the effects of sulfide treatment on P₃N₅/GaAs interfacial properties, GaAs-MIS diodes are also fabricated     

Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V     

Emission cross sections and spectroscopy of Ho3+ laserchannels in KGd(WO4)2 single crystal

The spectroscopic properties of Ho³⁺ laser channels in KGd(WO₄)₂ crystals have been investigated using optical absorption, photoluminescence, and lifetime measurements. The radiative lifetimes of Ho³⁺ have been calculated through a Judd-Ofelt (JO) formalism using 300-K optical absorption results. The JO parameters obtained were Ω₂=15.35×10^-20 cm², Ω ₄=3.79×10^-20 cm², Ω₆ =1.69×10^-20 cm². The 7-300-K lifetimes obtained in diluted (8·10¹⁸ cm^-3) KGW:0.1% Ho samples are: τ(⁵F₃)≈0.9 μs, τ( ⁵S₂)=19-3.6 μs, and τ(⁵F₅ )≈1.1 μs. For Ho concentrations below 1.5×10²⁰ cm^-3, multiphonon emission is the main source of non radiative losses, and the temperature independent multiphonon probability in KGW is found to follow the energy gap law τ_ph ^-1(0)=βexp(-αΔE), where β=1.4×10^-7 s^-1, and α=1.4×10³ cm. Above this holmium concentration, energy transfer between Ho impurities also contributes to the losses. The spectral distributions of the Ho³⁺ emission cross section σ_EM for several laser channels are calculated in σ- and π-polarized configurations. The peak a σ_EM values achieved for transitions to the ⁵I₈ level are ≈2×10^-20 cm² in the σ-polarized configuration, and three main lasing peaks at 2.02, 2.05, and 2.07 μm are envisaged inside the ⁵I₇→⁵I₈ channel     

Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

MOSFETs incorporating ZrO₂ gate dielectrics were fabricated. The I_DS-V_DS, I_DS-V_GS , and gated diode characteristics were analyzed to investigate the ZrO₂/Si interface properties. The interface trap density (D _it) was determined to be about 7.4times10¹² cm ^-2middoteV^-1 using subthreshold swing measurement. The surface-recombination velocity (s₀) and the minority carrier lifetime in the field-induced depletion region (tau _0,FIJ) measured from the gated diodes were about 3.5times10 ³ cm/s and 2.6times10^-6 s, respectively. The effective capture cross section of surface state (sigma_s) was determined to be about 5.8times10^-16 cm² using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxides was also made     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 Å

Electrical and reliability properties of ultrathin La₂O ₃ gate dielectric have been investigated. The measured capacitance of 33 Å La₂O₃ gate dielectric is 7.2 μF/cm² that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Å. Good dielectric integrity is evidenced from the low leakage current density of 0.06 A/cm² at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3×10¹⁰ eV^-1/cm², and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO₂      

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S