4H-SiC TSOB结势垒肖特基二极管的结构优化设计

室温下,沟槽底部有氧化物间隔的结势垒肖特基二极管的击穿电压达到2 009V,正向导通压降为2.5V,在正向偏压为5V时,正向电流密度为300A/cm2。在P型多晶硅掺杂的有源区生成双层SiO2间隔,以优化漂移区电场分布,正向导通压降为2.5V,击穿电压达到2 230V,耐压值提高11%。反向电压为1 000V时,反向漏电流密度比普通结构降低90%,有效地降低了器件的漏电功耗。普通结构的开/关电流比为2.56×103(1~500V),而改进结构的开/关电流比为3.59×104(1~500V)。     

一种隐埋缓冲掺杂层高压SBD器件新结构

提出了一种新型隐埋缓冲掺杂层(IBBD)高压SBD器件,对其工作特性进行了理论分析和模拟仿真验证。与常规高压SBD相比,该IBBD-SBD在衬底上方引入隐埋缓冲掺杂层,将反向击穿点从常规结构的PN结保护环区域转移到肖特基势垒区域,提升了反向静电释放(ESD)能力和抗反向浪涌能力,提高了器件的可靠性。与现有表面缓冲掺杂层(ISBD)高压SBD相比,该IBBD-SBD重新优化了漂移区的纵向电场分布形状,在保持反向击穿点发生在肖特基势垒区域的前提下,进一步降低反向漏电流、减小正向导通压降,从而降低了器件功耗。仿真结果表明,新器件的击穿电压为118 V。反向偏置电压为60 V时,与ISBD-SBD相比,该IBBD-SBD的漏电流降低了52.2%,正向导通电压更低。     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

垂直氮化镓沟槽栅极场效应管的优化设计

在传统的氮化镓沟槽栅极场效应管的基础上,通过引入AlGaN层,在异质结界面处形成二维电子气减小器件的导通电阻,并对漂移层的厚度和掺杂浓度进行讨论,使用TCAD软件对器件进行设计优化。最终优化后的漂移层厚度为6μm,掺杂浓度为5×10¹⁶ cm^-3。器件获得了较低的导通电阻R_on=0.47 mΩ·cm²,较高的击穿电压V_BR=2 880 V和品质因子FOM=17.6 GW·cm^-2。结果显示出了沟槽栅极垂直氮化镓场效应管在高压大电流应用场景下的优势。     

高k栅介质增强型β-Ga2O3 VDMOS器件的单粒子栅穿效应研究

以增强型β-Ga₂O₃ VDMOS器件作为研究对象,利用TCAD选择不同的栅介质材料作为研究变量,观察不同器件的单粒子栅穿效应敏感性。高k介质材料Al₂O₃和HfO₂栅介质器件在源漏电压200 V、栅源电压-10 V的偏置条件下能有效抵御线性能量转移为98 MeV·cm²/mg的重离子攻击,SiO₂栅介质器件则发生了单粒子栅穿效应(Single event gate rupture, SEGR)。采用HfO₂作为栅介质时源漏电流和栅源电流分别下降92%和94%,峰值电场从1.5×10⁷ V/cm下降至2×10⁵ V/cm,避免了SEGR的发生。SEGR发生的原因是沟道处累积了大量的空穴,栅介质中的临界电场超过临界值导致了击穿,而高k栅介质可以有效降低器件敏感区域的碰撞发生率,抑制器件内电子空穴对的进一步生成,降低空穴累积的概率。     

阳极刻蚀提升Ga2O3肖特基势垒二极管击穿特性

提出了一种采用阳极刻蚀提升Ga₂O₃肖特基势垒二极管(SBD)击穿特性的新方法。基于氢化物气相外延(HVPE)法生长的Ga₂O₃材料制备了Ga₂O₃纵向SBD。在完成阳极制备后，对阳极以外的Ga₂O₃漂移区进行了不同深度的刻蚀，刻蚀完成后，在器件表面生长了SiO₂介质层，随后制备了场板结构。测试结果显示，刻蚀后器件的比导通电阻小幅上升，而反向击穿电压均大幅提升。刻蚀深度为300 nm的β-Ga₂O₃ SBD具有最优特性，其比导通电阻(R_{on, sp})为2.5 mΩ·cm²,击穿电压(V_br)为1 410 V,功率品质因子(FOM)为795 MW/cm²。该研究为高性能Ga₂O₃ SBD的制备提供了一种新方法。     

Bi1.5Zn1.0 Nb1.5O7栅绝缘层的SiO2修饰对ZnO-TFTs性能的影响

具有高介电常数的栅绝缘层材料存在某种极化及耦合作用,使得ZnO-TFTs具有高的界面费米能级钉扎效应、大的电容耦合效应和低的载流子迁移率.为了解决这些问题,本文提出了一种使用SiO₂修饰的Bi_1.5Zn_1.0Nb_1.5O₇作为栅绝缘层的ZnO-TFTs结构,分析了SiO₂修饰对栅绝缘层和ZnO-TFTs性能的影响.结果表明,使用SiO₂修饰后,栅绝缘层和ZnO-TFTs的性能得到显著提高,使得ZnO-TFTs在下一代显示领域中具有非常广泛的应用前景.栅绝缘层的漏电流密度从4.5×10^-5A/cm²降低到7.7×10^-7A/cm²,粗糙度从4.52nm降低到3.74nm,ZnO-TFTs的亚阈值摆幅从10V/dec降低到2.81V/dec,界面态密度从8×10¹³cm^-2降低到9×10¹²cm^-2,迁移率从0.001cm²/（V·s）升高到0.159cm²/（V·s）.     

沟槽肖特基器件Si深槽刻蚀工艺

深硅刻蚀工艺是制造沟槽肖特基器件的关键技术.Si深槽的深度影响肖特基反向击穿电压,深槽的垂直度影响多晶Si回填效果,侧壁平滑度及深槽底部长草现象对器件的耐压性能影响显著.采用SF6/O2常温刻蚀工艺刻蚀Si深槽.研究了工艺压力、线圈功率、SF6/O2比例以及下电极功率等参数对沟槽深度均匀性和垂直度的影响.得到了使Si深槽形貌为槽口宽度略大于槽底,侧壁光滑,且沟槽深度均匀性为2.3％左右的工艺条件.利用该刻蚀工艺可实现沟槽多晶Si无缝回填.该工艺条件成功应用于沟槽肖特基器件制作中,反向击穿电压达到58 V,反向电压通48 V,漏电流为11.2 μA,良率达到97.55％.     

3 A/40 V新型肖特基势垒二极管的设计与研制

为提高传统肖特基二极管的击穿电压,减小了器件的漏电流,提高芯片利用率,文中设计研制了适合于裸片封装的新型肖特基势垒二极管(SBD)。利用Silvaco Tcad软件模拟,在器件之间采用PN结隔离,器件周围设计了离子注入形成的保护环,实现了在浓度和厚度分别为7.5×1012 cm-3和5 μm的外延层上,制作出了反向击穿电压45 V和正向导通压降0.45 V的3 A/45 V肖特基二极管,实验和仿真结果基本吻合。此外,还开发了改进SBD结构、提高其电特性的工艺流程。     

一种超结高压肖特基势垒二极管

改善反向击穿电压和正向导通电阻之间的矛盾关系一直以来都是功率半导体器件的研究热点之一。介绍了一种超结肖特基势垒二极管(SJ-SBD),将p柱和n柱交替构成的超结结构引入肖特基势垒二极管中作为耐压层,在保证正向导通电阻足够低的同时提高了器件的反向耐压。在工艺上通过4次n型外延和4次选择性p型掺杂实现了超结结构。基于相同的外延层厚度和相同的外延层杂质浓度分别设计和实现了常规SBD和SJ-SBD,测试得到常规SBD的最高反向击穿电压为110 V,SJ-SBD的最高反向击穿电压为229 V。实验结果表明,以超结结构作为SBD的耐压层能保证正向压降等参数不变的同时有效提高击穿电压,且当n柱和p柱中的电荷量相等时SJ-SBD的反向击穿电压最高。     

High voltage 4H-SiC Schottky barrier diodes

Characteristics of 4H-SiC Schottky barrier diodes with breakdown voltages up to 1000 V are reported for the first time. The diodes showed excellent forward I-V characteristics, with a forward voltage drop of 1.06 V at an on-state current density of 100 A/cm². The specific on-resistance for these diodes was found to be low (2×10 ^-3 Ω-cm² at room temperature) and showed a T ^1.6 variation with temperature. Titanium Schottky barrier height was determined to be 0.99 eV independent of the temperature. The breakdown voltage of the diodes was found to decrease with temperature     

A fully planarized 4H-SiC trench MOS barrier Schottky (TMBS)rectifier

A fully planarized 4H-SiC trench MOS barrier Schottky (TMBS) rectifier has been designed, fabricated and characterized for the first time. The use of a TMBS structure helps improve the reverse leakage current by more than three orders of magnitude compared to that of a planar Schottky rectifier. We have achieved a low reverse leakage current density of 6×10^-6 A/cm² and a low forward voltage drop of 1.75 V at 60 A/cm² for the TMBS rectifier. The static current-voltage (I-V) and switching characteristics of the TMBS rectifier have been measured at various temperatures. A barrier height of 1.0 eV and an ideality factor of 1.8 were extracted from the forward characteristics. The switching characteristics do not change with temperature indicating the essential absence of stored charge     

Lateral IGBT in thin SOI for high voltage, high speed power IC

A high voltage LIGBT built in ultra-thin silicon-on-insulator (SOI) with a linearly graded doping profile is reported. The highest breakdown voltage of 720 V was measured for an LIGBT built in 0.5 μm SOI with a 4 μm buried oxide. A forward voltage drop of 6 V at 100 Acm^-2 and a turn-off time of 140 ns have been achieved in the same device. Device forward voltage drop is very sensitive to the SOI thickness due to the recombination of carriers at the two silicon-silicon dioxide interfaces. An SOI thickness of 0.5 μm and an n-buffer doped to 10¹⁸ cm^-3 have been found to be a reasonable trade-off between the breakdown voltage and the forward voltage drop     

Turn-on process in 4H-SiC thyristors

Detailed turn-on measurements of 4H-Silicon Carbide (SiC) npnp thyristors are presented for a wide range of operating conditions. Comparisons with similarly-rated silicon and Gallium Arsenide thyristors show a superior rise time and pulsed turn-on performance of SiC thyristors. Rise time for a 400 V blocking voltage, 4 V forward drop (2.8×10³ A/cm²) SiC thyristor has been found to be of the order of 3-5 ns. Pulsed turn on measurements show a residual voltage of only 50 V when a current density of 10⁵ A/cm² (35 A) was achieved in 20 ns     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

Nonuniform and latchup current detection in lateral conductivitymodulated FETs

Three-dimensional effects on current distribution in lateral conductivity modulated power transistors such as the lateral insulated-gate bipolar transistor (LIGBT) are studied using the infrared microscopy technique. Nonuniform current distribution and the location of the latchup sites in these devices have been identified. This provides experimental insights into the design and optimization of these high-voltage power transistors. For optimized p⁺ anode LIGBT devices with a breakdown voltage of 600 V, a current density of 200 A/cm ² at a forward voltage of 2 V, which is comparable to the DMOS IGBT, and a latchup current density above 800 A/cm² have been obtained     

A high breakdown-voltage SiCN/Si heterojunction diode forhigh-temperature applications

Cubic crystalline p-SiCN films are deposited on n-Si(100) substrates to form SiCN/Si heterojunction diodes (HJDs) with a rapid thermal chemical vapor deposition (RTCVD) technique. The developed SiCN/Si HJDs exhibit good rectifying properties up to 200°C. At room temperature, the reverse breakdown voltage is more than 29 V at the leakage current density of 1.2×10^-4 A/cm². Even at 200°C, the typical breakdown voltage of SiCN/Si HJDs is still preserved about 5 V at the leakage current density of 1.47×10^-4 A/cm². These properties are better than the β-SiC on Si HJDs for high temperature applications     

A novel trench termination design for 100-V TMBS diode application

In this letter, a novel trench termination structure that can inhibit the reverse leakage current substantially and reduce the process cost is introduced. For trench type power devices, such as trench MOS barrier Schottky (TMBS) diodes, this new termination structure can be processed simultaneously with the active region without any additional mask. Simulation and experimental results show that TMBS diodes with this new termination structure can achieve a reverse blocking voltage of 100 V with a leakage current density as low as 8.4×10^-4 A/cm²     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C