电子产品静电放电失效分析与对策

介绍了静电放电的两种耦合路径,通过实际案例,分析了测试过程中遇到的静电放电原因,并分别采取了接地、隔离、提供能量泄放通道等整改措施.整改后的产品都通过了相关的测试.     

高原变电站35kV电缆选型的探究

阐述了高原35kV高压线缆在运行过程中,陆续出现的高压电缆绝缘层击穿、放电现象,针对该现象进行原因分析和查找,并提出相应整改方案,并在实际中运用验证整改方案的效果.     

静电放电参数对电极速度的相关性与机理分析

同步测量了带电人体手握金属小棒电极放电电流的参数和电极运动速度.金属小棒电极与靶电极相撞时的速度对放电电流参数(放电电流峰值、放电电流时间变化率的峰值、火花放电的弧长)的影响,用统计软件SPSS进行了考察,获得了在不同人体电压情况下小棒电极运动速度与放电参数的相关系数.结果表明:充电电压为0.3kV时,放电参数与电极运动速度无关.充电电压为0.5kV及其以上电压时,电极运动速度与放电电流峰值、电流最大上升斜率有极强的正相关性;与放电火花弧长有极强的负相关性.电极向靶的快速接近改变放电间隙的空气压强,改变间隙两端的电场强度,从而引起放电参数的显著变化.     

电子产品中静电防护问题研究

本文介绍了静电起电、静电放电(ESD)的机理及静电放电的危害,进一步阐述了人体感知静电和产品潜在损伤等问题及其产生的原因.针对静电积聚、静电敏感度和静电耦合能量等产生静电放电的前提条件,按照抑制起电、控制积聚的防护原则,提出了减少静电放电危害,提高电子产品可靠性的具体措施,在设计阶段对产品进行ESD防护网络设计,在生产...     

液晶屏幕抗静电分析与对策

液晶屏幕越来越多地应用在信息技术设备当中,但是液晶屏幕防静电技术却一直困扰着很多工程师.通过分析液晶屏幕显示原理,结合静电场理论,分析静电放电(ESD)对液晶屏幕的影响,并提供整改实例,简要介绍此类问题的处理方法.     

新一代液晶、智能化静电放电发生器

上海三基近日推出了一款液晶界面的智能化SKS-0220G和SKS-0230G静电放电发生器,其性能符合GB／T17626．2-2006的要求。·结构紧凑,小巧轻便,便于携带,为现场测试带来方便。·超高严酷度设计理念,提供了接触放电和空气放电超高测试电压裕度,可以满足所有通用静电抗扰度测试标准。SKS-0220G和SKS-0230G的最高输出电压分别达到20kV和30kV。     

某电子系统的ESD抗扰度性能研究

对某军用电子系统（简称被试系统）进行了静电放电（ESD）抗扰度试验,研究了不同放电模式下系统受ESD干扰情况。当放电电压低于2kV时,ESD对于被试系统基本不造成干扰;当放电电压超过2kV后,被测系统信号出现了过零点不正常、不翻转和死机三种现象。分析认为被试系统中检测仪在电磁兼容性（EMC）方面存在的问题,是影响整个被试系统抗扰度的主要原因。采取电磁防护加固措施能提高系统的ESD抗扰度性能。     

电子产品的防静电性能改进方法概述

从静电放电的起因开始,给出了国家标准规定的静电放电参数.对静电放电的耦合路径和防护方法进行了分析,以指导工程师在进行电路设计时,掌握如何防止静电放电对产品的影响.     

MOS器件的ESD失效

静电放电(ESD)对半导体器件,尤其是金属氧化物半导体(MOS)器件的影响日趋凸显,而相关的研究也是备受关注.综述了静电放电机理和3种常用的放电模型,遭受ESD应力后的MOS器件失效机理,MOS器件的两种失效模式;总结了ESD潜在性失效灵敏表征参量及检测方法;并提出了相应的静电防护措施.     

传输线理论分析静电放电电流

传输线理论分析了静电放电(ESD)发生器的放电过程,时域有限差分法(FDTD)模拟了放电电流,得到与IEC61000-4-2标准相符合的电流波形,并对影响电流波形的关键因素进行讨论.结果表明,静电放电发生器中电阻和连接线长度影响电流波形的上升时间;连接线的布置影响着电流波形的平滑性;不同的终端负载也对电流峰值有很大影响.该结论为静电放电发生器的设计提供了参考和建议.     

电子计量产品接触式静电放电的接地改良研究

在电子工业中,由于静电会损坏电子元器件、严重影响产品质量的问题尚未得到解决,该文对某电子产品（简称被试系统）进行了静电放电（ESD）抗扰度试验,研究了接触式静电放电模式下系统受ESD干扰的情况。当放电电压低于4.5KV时,ESD对于被试系统基本没有影响;当放电电压大于5KV时,受试设备出现蜂鸣器报警、死机现象。通过改进接地,使其抗压能力提高,并对比分析不同接地措施,对进一步改进静电接地提供参考和依据。     

Optimization of on-chip ESD protection structures for minimal parasitic capacitance

Diodes are key components in on-chip electrostatic discharge (ESD) protection design. As the operating frequency of the microchip being protected against the ESD continues to increase, the parasitic capacitance associated with the diodes in the ESD structure starts to impose problems for RF operation. This paper presents a systematic approach to optimize the diode structure for minimal parasitic capacitance based on the requirements of breakdown voltage and heat dissipation. Device simulator Atlas with mix-mode simulation capability is calibrated against measurement data and used to carry out the optimization. An optimized diode structure with a parasitic capacitance of less than 30 fF at an operating frequency of 10 GHz and ESD charging voltage of 1 kV has been suggested. Furthermore, a case study to implement and optimize the ESD protection structure based on an existing 0.13-μm CMOS technology has been presented and verified.     

$hbox{VO}_{2}$ Thin-Film Varistor Based on Metal-Insulator Transition

For electronic applications, we have fabricated VO₂ thin-film variable resistors (varistors) using metal-insulator transition regarded as the abrupt current jump. The increase of the number of parallel stripe patterns in the varistor leads to the increase in current below a current-jump voltage, which endures a high surge voltage with high current and short rising time. Electrostatic discharge (ESD) experiments show that the varistic coefficient of 500 is larger than 30-80, which is known for commercial ZnO varistors. In overvoltage-protection tests applying high ESD voltages up to 3.3 kV to a varistor, the maximum response voltage is lower than 200 V at an ESD voltage of 1600 V, and the electronic response time is less than 20 ns. This is sufficient to protect a device perfectly.     

ESD protection design for 1- to 10-GHz distributed amplifier in CMOS technology

Two distributed electrostatic discharge (ESD) protection schemes are presented and applied to protect distributed amplifiers (DAs) against ESD stresses. Fabricated in a standard 0.25-/spl mu/m CMOS process, the DA with the first protection scheme of the equal-sized distributed ESD (ES-DESD) protection scheme, contributing an extra 300 fF parasitic capacitance to the circuit, can sustain the human-body model (HBM) ESD level of 5.5 kV and machine-model (MM) ESD level of 325 V and exhibits the flat-gain of 4.7 /spl plusmn/ 1 dB from 1 to 10 GHz. With the same amount of parasitic capacitance, the DA with the second protection scheme of the decreasing-sized distributed ESD (DS-DESD) protection scheme achieves better ESD robustness, where the HBM ESD level over 8 kV and MM ESD level is 575 V, and has the flat-gain of 4.9 /spl plusmn/ 1.1 dB over the 1 to 9.2-GHz band. With these two proposed ESD protection schemes, the broad-band RF performances and high ESD robustness of the DA can be successfully codesigned to meet the application specifications.     

Failure mechanisms of discrete protection device subjected to repetitive electrostatic discharges (ESD)

High reliability electronic devices need to sustain thousands of electrostatic discharge (ESD) stresses during their lifetime. In this paper, it is demonstrated that repetitive ESD stresses on a protection device such as a bidirectional diode induce progressive defects into the silicon bulk. With “Sirtl etch” failure analysis technique, the defects could be localized quite precisely at the peripheral in/out junctions. The degradation mechanisms during repetitive IEC 61000-4-2 pulses have been investigated on a protection diode with the objective of improving the design for sustaining 1000 pulses at 10 kV level.     

静电放电(ESD)在电子装联中的危害及防护

通过对静电及静电放电(ESD)的简单介绍,提出了在电子装联中进行静电防护的必要性和基本思路.     

ESD对RuO2厚膜电阻阻值的影响

采用静电放电(Electrostatic discharge,ESD)发生器对RuO2厚膜电阻直接放电,研究了电阻阻值变化率与电阻尺寸、阻值和ESD条件的关系。结果表明:厚膜电阻阻值受ESD作用而下降;相同ESD及阻值条件下的阻值变化率随电阻尺寸的增大而减小;相同电阻的阻值变化率随ESD电压的增大而增大;10kΩ左右的厚膜电阻在ESD作用下的阻值变化率最大,阻值变化率随着阻值的减小和增大而呈减小趋势;对10kΩ厚膜电阻反复施加不断增大的ESD电压,除宽度尺寸为0.45mm的电阻阻值在8～10kV之间出现一次回升外,电阻阻值逐步下降。     

静电放电作用下微波双极型晶体管的失效机理研究

通过理论建模和试验测试的方法研究了多指结构微波双极型晶体管在静电放电作用下的热稳定性和电稳定性。选择2SC3356作为受试器件,对100个测试样本进行人体模型静电放电注入实验,并从器件内部电场强度、电流密度和温度分布变化出发,用二维器件级仿真软件辅助分析了在静电放电应力下其内在损伤过程与机理。由于指间热耦合的存在,雪崩电流在各指上分布不均,局部的电流拥挤和过热效应会导致晶格损伤。试验结果表明,由于特殊的物理结构,受试器件对静电放电最敏感的端对并不是EB结,而是CB结,当静电放电电压增大到1.3KV时,CB结首先损坏。失效分析进一步表明静电放电引起的失效机理通常是介质层的击穿和局部铝硅共晶体的过热融化。静电放电注入实验的过程中存在积累效应,多次低强度的注入测试会导致潜在性失效并使器件性能大幅下降。     

Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard

A hardware/firmware co-design solution in an 8-bits microcontroller has been proposed to practically fix the system-level electrostatic discharge (ESD) issue on the keyboard products. By including the especial ESD sensors and an additional ESD flag into the chip, the fast electrical transient due to the system-level ESD zapping on the keyboard can be detected. The firmware stored in the ROM of the 8-bits microcontroller is designed to automatically check the ESD flag to monitor the abnormal conditions in system operations. If the keyboard is upset or locked up by a system-level ESD transient, the microcontroller can be quickly recovered to a known and stable state. The 8-bits microcontroller with such a hardware/firmware co-design solution has been fabricated in a 0.45-μm CMOS process. The system-level ESD susceptibility of the keyboard with this 8-bits microcontroller has been improved from the original ±2 kV (±4 kV) to become greater than ±8 kV (±15 kV) in the contact-discharge (air-discharge) ESD zapping.     

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

This paper reports a real case of electrostatic discharge (ESD) improvement on a complementary metal oxide semiconductor integrated circuit (IC) product with multiple separated power pins. After ESD stresses, the internal damage have been found to locate at the interface circuit connecting between different circuit blocks with different power supplies. Some ESD designs have been implemented to rescue this IC product to meet the required ESD specification. By adding only an extra ESD clamp N-channel metal oxide semiconductor with a channel width of 10 /spl mu/m between the interface node and the ground line, the human-body-model (HBM) ESD level of this IC product can be improved from the original 0.5 to 3 kV. By connecting the separated vertical sync signal (VSS) power lines through the ESD conduction circuit to a common VSS ESD bus realized by the seal ring, the HBM ESD level of the enhanced version IC product with 12 separated power supplies pairs can be significantly improved from original 1 kV up to > 5 kV, without the noise coupling issue.