Low Complexity Minimum Mean Square Error Channel Estimation for Adaptive Coding and Modulation Systems

Performance of the Adaptive Cod- ing and Modulation （ACM） strongly depends on the retrieved Channel State Information （CSI）, which can be obtained using the chan- nel estimation techniques relying on pilot sy- mbol transmission. Earlier analysis of methods of pilot-aided channel estimation for ACM systems were relatively little. In this paper, we investigate the performance of CSI prediction using the Minimum Mean Square Error （MMSE） channel estimator for an ACM system. To solve the two problems of MMSE： high compu- tational operations and oversimplified assum- ption, we then propose the Low-Complexity schemes （LC-MMSE and Recursion LC-MMSE （R-LC-MMSE））. Computational complexity and Mean Square Error （MSE） are presented to evaluate the efficiency of the proposed algo- rithm. Both analysis and numerical results sh- ow that LC-MMSE performs close to the well- known MMSE estimator with much lower com- plexity and R-LC-MMSE improves the appli- cation of MMSE estimation to specific cir- cumstances.     

互联网流量的结构特性:重叠社团和相关性(英文)

There is an increasing number of Internet applications, which leads to an increasing network capacity and availability. Internet traffic characterisation and application identification are, therefore, more important for efficient network management. In this paper, we construct flow graphs from detailed Internet traffic data collected from the public networks of Internet Service Providers. We analyse the community structures of the flow graph that is naturally formed by different applications. The community size, degree distribution of the community, and community overlap of 10 Internet applications are investigated. We further study the correlations between the communities from different applications. Our results provide deep insights into the behaviour Internet applications and traffic, which is helpful for both network management and user behaviour analysis.     

Real-Time Upstream Services Demonstration in Orthogonal Frequency Division Multiplexing- Passive Optical Network System

Abstract： Real-time digital service and mul- timedia service upstream transmission in Dig- ital Signal Processing （DSP）-based Orthogo- nal Frequency Division Multiplexing-Passive Optical Network （OFDM-PON） is experimen- tally demonstrated with Centralised Light Sou- rce （CLS） configuration in this paper. After transmitted over 25 km Standard Single Mode Fibre （SSMF） with -16.5 dBm optical power at receiver, the Bit Error Rate （BER） is 9.5 ×10^-11. The implementations of digital domain up-conversion and down-conversion based on Field Programmable Gate Array （FPGA） are int- roduced, which can reduce the cost of In-ph- ase and Quadrature （IQ） radio frequency mix- ers utilised at transmitter and receiver. A car- rier synchronization algorithm is implemented for compensating carrier offset. A channel eq- ualization algorithm is adopted for compen- sating the damage of channel. A new structure of Frequency Synchronization Unit （FSU） des- igned in FPGA is also proposed to cope with the frequency shifting at receiver.     

10-Gb/s Transmission in WDM PON Employing Reflective Semiconductor Optical Amplifier and Fibre Bragg Grating Equaliser

We propose a 10-Gb/s Wavelength- Division-Multiplexed Passive Optical Network （WDM-PON） scheme with upstream transmi- ssion employing Reflective Semiconductor Op- tical Amplifier （RSOA） and Fibre Bragg Gra- ting （FBG） optical equaliser. Transmissions of 10-Gb/s non return-to-zero signals using a 1.2- GHz RSOA and FBG optical equaliser with different setups are demonstrated. Significant performance improvement and 40-kin standard single mode fibre transmission are achieved using FBG optical equaliser and Remotely Pum- ped Erbium-Doped Fibre Amplifier （RP-EDFA）, where they are used to equalise the output of the band-limited RSOA and amplify the seed light and upstream signal, respectively.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

应用于2.4GHz无线传感网的超低功耗射频接收前端设计

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network （WSN） in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate （CG） LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure （NF） at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point （IPldB） at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.     

Large-Scale Traffic Characterization of Chinese Multimedia Messaging Service Using Hadoop

Recently, there have been many mo- bile value-added services in the Chinese mo- bile telecommunication market nowadays. Am- ong them, the characteristics of Multimedia Mes- saging Service （MMS） have not yet been fully understood. In this paper, with the help of a cloud computing platform, we investigated the flow-level charactefistcs of Chinese MMS. All of the experimental data were collected by the TMS equipment deployed in a major node in Sou- them China. The collection time spanned six mo- nths. We performed high-level analysis to show the basic distributions of MMS characteristics. Then, by analysing the detailed MMS features, we determined the distribution of personal MMS, and made a comprehensive comparison between 2G and 3G MMS. Finally, we tried to build a model on the personal MMS inter-arrival time, and we found that the Weibull distribution was optimum.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

Traffic Labeller： Collecting Internet Traffic Samples with Accurate Application Information

Traffic classification research has been suffering from a trouble of collecting acc- urate samples with ground truth. A model named Traffic Labeller （TL） is proposed to solve this problem. TL system captures all user socket calls and their corresponding applica- tion process information in the user mode on a Windows host. Once a sending data call has been captured, its 5-tuple {source IP, destina- tion IP, source port, destination port and tra- nsport layer protocol}, associated with its ap- plication information, is sent to an intermedi- ate NDIS driver in the kernel mode. Then the intermediate driver writes application type inf- ormation on TOS field of the IP packets which match the 5-tuple. In this way, each IP packet sent from the Windows host carries their ap- plication information. Therefore, traffic sam- ples collected on the network have been lab- elled with the accurate application information and can be used for training effective traffic classification models.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

用于流水线ADC的频率自适应可编程MDAC电路

A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

多层铜布线CMP后表面残留CuO颗粒的去除研究

This article introduces the removal technology of CuO particles on the post CMP wafer surface of multi-layered copper. According to the Cu film corrosion curve with different concentrations of HEO2 and the effect curve of time on the growth rate of CuO film, CuO film with the thickness of 220 nm grown on Cu a surface was successfully prepared without the interference of CuC12.2H20. Using the static corrosion experiment the type of chelating agent （FA/O II type chelating agent） and the concentration range （10-100 ppm） for CuO removal was determined, and the Cu removal rate was close to zero. The effect of surfactant on the cleaning solution properties was studied, and results indicated that the surfactant has the effect of reducing the surface tension and viscosity of the cleaning solution, and making the cleaning agent more stable. The influence of different concentrations of FA/O I type surfactant and the mixing of FA/O II type chelating agent and FA/O I type surfactant on the CuO removal effect and the film surface state was analyzed. The experimental results indicated that when the concentration of FA/O I type surfactant was 50 ppm, CuO particles were quickly removed, and the surface state was obviously improved. The best removal effect of CuO on the copper wiring film surface was achieved with the cleaning agent ratio of FA/O II type chelating agent 75 ppm and FA/O I type surfactant 50 ppm. Finally, the organic residue on the copper pattern film after cleaning with that cleaning agent was detected, and the results showed that the cleaning used agent did not generate organic residues on the film surface, and effectively removes the organic residue on the water.     

基于动态定价的帧聚合策略(英文)

Frame aggregation is a wireless link optimization mechanism that aims to reduce transmission overheads by sending multiple frames as the payload of a single MAC frame. It is considered as one of the most efficient methods to improve the wireless channel utilization and the throughput of wireless networks.The static assignment of frame aggregation parameters can result in delay penalties due to variations in traffic type. We propose a frame aggregation scheme which is based on dynamic pricing and queue scheduling for a multitraffic scenario. The scheme adopts a dynamic differential pricing scheme for different types of traffic. Meanwhile, it polls buffer queues in accordance with the optimal aggregation weight factors to maximise the network revenue.Simulation results indicate that the proposed frame aggregation scheme can effectively improve the network revenue and the average throughput, while guaranteeing the delay requirements of all types of traffic.     

Secure Network Coding Based on Lattice Signature

To provide a high-security guaran- tee to network coding and lower the comput- ing complexity induced by signature scheme, we take full advantage of homomorphic prop- erty to build lattice signature schemes and sec- ure network coding algorithms. Firstly, by means of the distance between the message and its sig- nature in a lattice, we propose a Distance-bas- ed Secure Network Coding （DSNC） algorithm and stipulate its security to a new hard problem Fixed Length Vector Problem （FLVP）, which is harder than Shortest Vector Problem （SVP） on lattices. Secondly, considering the bound- ary on the distance between the message and its signature, we further propose an efficient Bo- undary-based Secure Network Coding （BSNC） algorithm to reduce the computing complexity induced by square calculation in DSNC. Sim- ulation results and security analysis show that the proposed signature schemes have stronger unforgeability due to the natural property of lattices than traditional Rivest-Shamir-Adleman （RSA）-based signature scheme. DSNC algo- rithm is more secure and BSNC algorithm greatly reduces the time cost on computation.