Design principles for light trapping in thin silicon films with embedded dielectric nanoparticles

We investigate the light‐trapping effects of dielectric nanoparticles embedded within the active semiconductor layer of a thin‐film solar cell. The baseline model consists of a 1·0 µm slab of crystalline silicon on an aluminum back contact topped with a 75 nm Si₃N₄ anti‐reflective coating. Using finite‐difference time‐domain simulations, we calculate the absorption gain due to a periodic array of SiO₂ nanospheres with characteristic depth, diameter, and pitch. Under optimal conditions, absorption gain due to embedded spheres can reach as high as 23·4% relative to the baseline geometry. Using Au‐core/SiO₂‐shell nanoparticles, it is even possible to reach 30%. We then infer a series of design principles from our data that include trade‐offs between broadband scattering efficiency, poor absorption at long wavelengths, and semiconductor displacement. We also find that the optimal spacing between particles is approximately 400 nm. Above this distance, each scatterer acts in near isolation from any neighboring particles, and absorption gain is approximately linear with area coverage. Such gains are also expected for disordered as well as ordered arrays. These results demonstrate the potential of embedded dielectric nanoparticles as a tool for enhancing carrier generation in thin silicon solar cells. Copyright © 2011 John Wiley & Sons, Ltd.     

Controlling the diameter of silicon nanowires grown using a tin catalyst

Silicon nanowires were grown on ITO-coated glass substrates via a pulsed plasma enhanced chemical vapor deposition method, using tin as a catalyst. The thin films of catalyst, with different thicknesses in the range 10–100 nm, were deposited on the substrates by a thermal evaporation method. The effect of the thickness of the thin film catalyst on the morphology of the silicon nanowires was investigated. The scanning/transmission electron microscopy images showed that the wire diameter increased as the thickness of the thin film catalyst increased. The nanowires grown using a thin film thickness of 10 nm were inhomogeneous in diameter, whereas the other thicknesses led to an increase in the homogeneity of the diameters of the nanowires. The dominant wire diameter of the grown silicon nanowires ranged from 70 to 80 nm with 10 nm catalyst thin film thickness, and increased to a range of 190–200 nm with 100 nm catalyst thin film thickness.     

Scaling the Aspect Ratio of Nanoscale Closely Packed Silicon Vias by MacEtch: Kinetics of Carrier Generation and Mass Transport

Metal‐assisted chemical etching (MacEtch) has shown tremendous success as an anisotropic wet etching method to produce ultrahigh aspect ratio semiconductor nanowire arrays, where a metal mesh pattern serves as the catalyst. However, producing vertical via arrays using MacEtch, which requires a pattern of discrete metal disks as the catalyst, has often been challenging because of the detouring of individual catalyst disks off the vertical path while descending, especially at submicron scales. Here, the realization of ordered, vertical, and high aspect ratio silicon via arrays by MacEtch is reported, with diameters scaled from 900 all the way down to sub‐100 nm. Systematic variation of the diameter and pitch of the metal catalyst pattern and the etching solution composition allows the extraction of a physical model that, for the first time, clearly reveals the roles of the two fundamental kinetic mechanisms in MacEtch, carrier generation and mass transport. Ordered submicron diameter silicon via arrays with record aspect ratio are produced, which can directly impact the through‐silicon‐via technology, high density storage, photonic crystal membrane, and other related applications.     

Dendrite‐Assisted Growth of Silicon Nanowires in Electroless Metal Deposition

This article concerns the detailed investigations on the silver dendrite‐assisted growth of single‐crystalline silicon nanowires, and their possible self‐assembling nanoelectrochemistry growth mechanism. The growth of silicon nanowires was carried out through an electroless metal deposition process in a conventional autoclave containing aqueous HF and AgNO₃ solution near room temperature. In order to explore the mechanism and prove the centrality of silver dendrites in the growth of silicon nanowires, other etching solution systems with different metal species were also investigated in this work. The morphology of etched silicon substrates strongly depends upon the composition of the etching solution, especially the metal species. Our experimental results prove that the simultaneous formation of silver dendrites is a guarantee of the preservation of free‐standing nanoscale electrolytic cells on the silicon substrate, and also assists in the final formation of silicon nanowire arrays on the substrate surface.     

Orientation‐Controlled Selective‐Area Epitaxy of III–V Nanowires on (001) Silicon for Silicon Photonics

Monolithic integration of III–V nanowires on silicon platforms has been regarded as a promising building block for many on‐chip optoelectronic, nanophotonic, and electronic applications. Although great advances have been made from fundamental material engineering to realizing functional devices, one of the remaining challenges for on‐chip applications is that the growth direction of nanowires on Si(001) substrates is difficult to control. Here, catalyst‐free selective‐area epitaxy of nanowires on (001)‐oriented silicon‐on‐insulator (SOI) substrates with the nanowires aligned to desired directions is proposed and demonstrated. This is enabled by exposing {111} planes on (001) substrates using wet chemical etching, followed by growing nanowires on the exposed planes. The formation of nanowire array‐based bottom‐up photonic crystal cavities on SOI(001) and their coupling to silicon waveguides and grating couplers, which support the feasibility for on‐chip photonic applications are demonstrated. The proposed method of integrating position‐ and orientation‐controllable nanowires on Si(001) provides a new degree of freedom in combining functional and ultracompact III–V devices with mature silicon platforms.     

Densely Packed Arrays of Ultra‐High‐Aspect‐Ratio Silicon Nanowires Fabricated using Block‐Copolymer Lithography and Metal‐Assisted Etching

Metal‐assisted etching is used in conjunction with block‐copolymer lithography to create ordered and densely‐packed arrays of high‐aspect‐ratio single‐crystal silicon nanowires with uniform crystallographic orientations. Nanowires with diameters and spacings down to 19 nm and 10 nm, respectively, are created as either continuous carpets or as carpets within trenches. Wires with aspect ratios up to 220 are fabricated, and capillary‐induced clustering of wires is eliminated through post‐etching critical point drying. The wires are single crystals with 〈100〉 axis directions. The distribution of wire diameters is narrow and closely follows the size distribution of the block copolymer, with a standard deviation of 3.12 nm for wires of mean diameters 22.06 nm. Wire arrays formed in carpets and in channels have hexagonal order with good fidelity to the block copolymer pattern. Fabrication of wires in topographic features demonstrates the ability to accurately control wire placement. Wire arrays made using this new process will have applications in the creation of arrays of photonic and sensing devices.     

Well‐Aligned ZnO Nanowire Arrays Fabricated on Silicon Substrates

Arrays of well‐aligned single‐crystal zinc oxide (ZnO) nanowires of uniform diameter and length have been synthesized on a (100) silicon substrate via a simple horizontal double‐tube system using chemical vapor transport and condensation method. X‐ray diffraction and transmission electron microscopy (TEM) characterizations showed that the as‐grown nanowires had the single‐crystal hexagonal wurtzite structure with detectable defects and a <0002> growth direction. Raman spectra revealed phonon confinement effect when compared with those of ZnO bulk powder, nanoribbons, and nanoparticles. Photoluminescence exhibited strong ultraviolet emission at 3.29 eV under 355 nm excitation and green emission at 2.21 eV under 514.5 nm excitation. No catalyst particles were found at the tip of the nanowires, suggesting that the growth mechanism followed a self‐catalyzed and saturated vapor–liquid–solid (VLS) model. Self‐alignment of nanowires was attributed to the local balance and steady state of vapor flow at the substrate. The growth technique would be of particular interest for direct integration in the current silicon‐technology‐based optoelectronic devices.     

Plasmon-loss imaging of chains of crystalline-silicon nanospheres and silicon nanowires

Nanostructures in chains of crystalline-silicon nanospheres and silicon nanowires were investigated using energy-filtered transmission electron microscopy (TEM). Observation of the shape of the silicon nanospheres in the chains provided the direct evidence that the chains were formed via the surface oxidation process, which may preferentially work at the necks. The diverse nanostructures in silicon nanowires were revealed, and we found smooth-shaped wires which have periodically modulated silicon cores. Nanostructures in wire-chain transition regions were also investigated for the first time. The wire-chain transition is not a simple junction of a silicon nanowire and a chain of silicon nanospheres, but has a periodically modulated silicon core in the wire region near the transition position.     

Direct electrodeposition of highly ordered magnetic nickel nanowires on silicon wafer

Highly ordered nickel nanowire (50 and 12 nm in diameter) arrays were successfully deposited into the nanoporous alumina template film on a gold-coated silicon wafer. The electrodeposited nickel nanowires have a preferred (220) fibre texture, that is the [110] direction parallel to the wire axis. With electropolishing, nanoporous alumina template with ordered and uniform pores was prepared by anodisation. By complete removal of the barrier layer and careful control of electrodeposition procedures, nearly 100% pore filling of uniform nanowires can be directly deposited onto the Au-coated silicon substrate, therefore no pattern transfer is necessary and incorporation of these nanowires into silicon-based devices is readily possible     

Hierarchically Ordered Arrays of Noncircular Silicon Nanowires Featured by Holographic Lithography Toward a High‐Fidelity Sensing Platform

A novel, highly uniform and tunable hybrid plasmonic array is created via ion‐milling, catalytic wet‐etching and electron‐beam evaporation, using a holographically featured structure as a milling mask. A simple and low‐cost prism holographic lithography (HL) technique is applied to create an unprecedentedly coordinated array of elliptic gold (Au) holes, which act as the silicon (Si) etching catalyst in the reaction solution used to fabricate an elliptic silicon nanowire (SiNW) array; here, the SiNWs are arrayed hierarchically in such a way that three SiNWs are triangularly coordinated, and the triangles are arranged hexagonally. After removing the polymeric mask and metal thin film, the highly anisotropic thick Au film is deposited on the SiNW arrays. This hybrid substrate shows tunable optical properties in the near‐infrared (NIR) region from 875 nm to 1030 nm and surface‐enhanced Raman scattering (SERS) activities; these characteristics depend on the catalytic wet etching time, which changes the size of the vertical gap between the Au thick films deposited separately on the SiNWs. In addition, lateral interparticle coupling induces highly intensified SERS signals with good homogeneity. Finally, the Au‐capped elliptical SiNW arrays can be hierarchically patterned by combining prism HL and conventional photolithography, and the highly enhanced fluorescence intensity associated with both the structural effects and the plasmon resonances is investigated.     

A Three Component Self‐Assembled Epitaxial Nanocomposite Thin Film

A self‐assembled three phase epitaxial nanocomposite film is grown consisting of ≈3 nm diameter fcc metallic Cu nanorods within square prismatic SrO rocksalt nanopillars in a Sr(Ti,Cu)O_3‐δ perovskite matrix. Each phase has an epitaxial relation to the others. The core–shell‐matrix structures are grown on SrTiO₃ substrates and can also be integrated onto Si using a thin SrTiO₃ buffer. The structure is made by pulsed laser deposition in vacuum from a SrTi_0.75Cu_0.25O₃ target, and formed as a result of the limited solubility of Cu in the perovskite matrix. Wet etching removes the 3 nm diameter Cu nanowires leaving porous SrO pillars. The three‐phase nanocomposite film is used as a substrate for growing a second epitaxial nanocomposite consisting of CoFe₂O₄ spinel pillars in a BiFeO₃ perovskite matrix, producing dramatic effects on the structure and magnetic properties of the CoFe₂O₄. This three‐phase vertical nanocomposite provides a complement to the well‐known two‐phase nanocomposites, and may offer a combination of properties of three different materials as well as additional avenues for strain‐mediated coupling within a single film.     

Fabrication of Single‐Crystalline Silicon Nanowires by Scratching a Silicon Surface with Catalytic Metal Particles

A novel strategy for preparing large‐area, oriented silicon nanowire (SiNW) arrays on silicon substrates at near room temperature by localized chemical etching is presented. The strategy is based on metal‐induced (either by Ag or Au) excessive local oxidation and dissolution of a silicon substrate in an aqueous fluoride solution. The density and size of the as‐prepared SiNWs depend on the distribution of the patterned metal particles on the silicon surface. High‐density metal particles facilitate the formation of silicon nanowires. Well‐separated, straight nanoholes are dug along the Si block when metal particles are well dispersed with a large space between them. The etching technique is weakly dependent on the orientation and doping type of the silicon wafer. Therefore, SiNWs with desired axial crystallographic orientations and doping characteristics are readily obtained. Detailed scanning electron microscopy observations reveal the formation process of the silicon nanowires, and a reasonable mechanism is proposed on the basis of the electrochemistry of silicon and the experimental results.     

基于MEMS工艺制作的硅纳米线及其电学性质

通过运用Si3N4和SiO2作掩膜,采用各向同性和各向异性腐蚀液,利用硅的腐蚀自停止特性,实现了硅梁的纳米宽度控制,同时利用多次氧化在SOI材料上实现了纳米厚度控制,最终成功批量制作了硅纳米线.扫描电镜观测表明,制备的纳米线厚度和宽度都可严格控制在100nm以下,最细的纳米线宽度可以达到20nm.同批样品的宽度变化范围在20%以内.大气中对其电学特性测量表明,剥离了表面氧化层的纳米线的电阻会随放置时间的增长而逐渐增大.进一步实验分析发现水分吸附在其电阻变化中起了重要的作用.     

光电化学腐蚀法制备高长径比硅微通道

在高长径比硅微通道光电化学腐蚀中,需要根据通道尺寸要求实时修正腐蚀电流.研究了物质输运、暗电流对腐蚀电流控制的影响,并提出了腐蚀电流的控制曲线.根据电解液扩散方程和边界条件,推导出通道尖端处HF质量分数与通道长度的关系.根据腐蚀后的暗扫描I-V曲线计算出暗电流密度.与腐蚀电流密度相比,阴离子表面活性剂的暗电流可忽略不计,进而获得了腐蚀电流修正曲线.根据腐蚀电流修正曲线,通过控制光照强度制备出高长径比(大于60)的等径硅微通道阵列.对修正的腐蚀电流进行调整,制备出通道尺寸空间周期性变化的硅微通道结构.研究结果可为高长径比硅微通道的制备提供技术方法.     

金纳米粒子作掩模的硅纳米柱阵列的加工

利用自组装的方法在硅基片表面形成一层均匀的金纳米粒子掩模,分析了偶联剂对自组装的影响,以金纳米粒子作掩模进行反应离子刻蚀,研究了刻蚀时间对硅纳米柱阵列的影响,提供了一种简单、便宜并且有效的在硅基底上大面积形成纳米柱阵列的纳米加工方法。实验中发现,超过一定刻蚀时间时,有过刻蚀现象发生,在120 s刻蚀时间下,得到了直径小于20 nm,深宽比高达10∶1以上规则、致密、大面积分布的硅纳米柱或硅纳米锥状结构。     

High-Temperature Performance of Stacked Silicon Nanowires for Thermoelectric Power Generation

Deep reactive-ion etching at cryogenic temperatures (cryo-DRIE) has been used to produce arrays of silicon nanowires (NWs) for thermoelectric (TE) power generation devices. Using cryo-DRIE, we were able to fabricate NWs of large aspect ratios (up to 32) using a photoresist mask. Roughening of the NW sidewalls occurred, which has been recognized as beneficial for low thermal conductivity. Generated NWs, which were 7 μm in length and 220 nm to 270 nm in diameter, were robust enough to be stacked with a bulk silicon chip as a common top contact to the NWs. Mechanical support of the NW array, which can be created by filling the free space between the NWs using silicon oxide or polyimide, was not required. The Seebeck voltage, measured across multiple stacks of up to 16 bulk silicon dies, revealed negligible thermal interface resistance. With stacked silicon NWs, we observed Seebeck voltages that were an order of magnitude higher than those observed for bulk silicon. Degradation of the TE performance of silicon NWs was not observed for temperatures up to 470°C and temperature gradients up to 170 K.     

Electric‐Driven Rotation of Silicon Nanowires and Silicon Nanowire Motors

In this work, the first highly controllable assembly and rotation of silicon nanowires and nanomotors in suspension are reported. Si and Si composite nanowires are fabricated with precisely controlled dimensions via colloidal assisted catalytic etching. The nanowires can be rotated with deterministic speed and chirality. The rotation speed and orientation not only depend on the applied AC electric frequency, but also on the electronic type, geometry, surface coating, as well as the electric conductance of suspension mediums. Theoretical analysis is used to understand the rotation of Si nanowires, and also the electric resistivity of Si nanowires is determined from their mechanical rotation. The Si nanowires are precisely assembled into nanomotors that can be rotated with controlled speeds and orientations at prescribed locations. This work provides a new paradigm for designing and actuating various Si‐based nanoelectromechanical system (NEMS) devices, which are relevant to man‐made nanomotors, nanorobots, and nanoengines.     

Macroporous Silicon Microcavities for Macromolecule Detection

Macroporous silicon microcavities for detection of large biological molecules have been fabricated from highly doped n‐type silicon. Well‐defined controllable pore sizes up to 120 nm have been obtained by systematically optimizing the etching parameters. The dependence of the sensor sensitivity on pore size is discussed. Excellent infiltration inside these macroporous silicon microcavities is demonstrated using 60 nm diameter latex spheres and rabbit IgG (150 kDa; 1Da = 1 g mol^–1). The sensing performance of the device is tested using a biotin/streptavidin couple, and protein concentration down to 1–2 μM (equivalent to 0.3 ng mm^–2) could be detected. Simulations show that the sensitivity of the technique is currently approximately 1–2 % of a protein monolayer.     

MBE growth and Structural Properties of InAs and InGaAs Nanowires with Different Mole Fraction of In on Si and Strongly Mismatched SiC/Si(111) Substrates

The possibility of InAs nanowires MBE growth on silicon (111) substrates with a nanometer buffer layer of silicon carbide has been demonstrated for the first time. The NWs diameter turned out to be smaller than on the silicon substrate—the minimum of NWs diameter was less than 10 nm. In addition, dependence of structural properties of InGaAs nanowires on composition was studied.

     

x光纳米光刻掩模的离子束制备法

重离子束轰击聚碳酸酯后,对样品进行陈化和紫外线照射敏化,在优化条件下蚀刻后得到纳米孔径核孔膜。利用电化学沉积技术在核孔膜中制备了最小孔径为30纳米的铜纳米线。获得的铜纳米线/聚碳酸酯可以作为x光纳米光刻的掩模。