可配置LDPC译码器中低复杂度移位网络的设计

针对可配置LDPC译码器,提出了一种低复杂度的移位网络结构,明显降低了硬件实现的复杂度。基于结构化LDPC译码器的两个特点:输入端的个数是一个常数的倍数、所有移位都是循环移位,提出易于实现且延迟很小的移位网络控制信号生成算法。此外,针对IEEE 802.16e标准的LDPC译码器,设计了采用这种结构的移位电路。基于SMIC 130nm工艺进行仿真,综合结果表明,该电路占用的芯片面积为0.11mm2,最高频率为430MHz。     

A Flexible LDPC/Turbo Decoder Architecture

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm². The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.     

Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding

This paper proposes a flexible QC-LDPC decoder to support on-line matrix downloading. Its applications include IEEE 802.16e, 802.11n/ac/ax, and other advanced standards. Via TSMC 40-nm technology, the flexible architecture only has an area of 0.415 mm². The according power dissipation is 84.68 mW at maximal clock frequency of 1.0 GHz. It is successfully verified with 3 LDPC codes pre-defined in IEEE 802.11n/ac/ax.     

Operation reduced low‐density parity‐check decoding algorithms for low power communication systems

Decoding operation reduction algorithms on min‐sum layered low‐density parity‐check (LDPC) decoders are proposed in this paper. Our algorithm freezes selected operations in high reliable nodes to reduce power while preserving error correcting performance. Both memory accesses and active node switching activities can be reduced. A novel node refresh mechanism reactivates frozen nodes to minimize coding gain degradation. We propose three decoding operation reduction algorithm variations to trade‐off complexity and operation reduction for LDPC decoders with different degrees of parallelism and memory requirement. Simulation results show that the number of LDPC decoding operations is reduced across all SNR ranges. The decoding convergence speed is not affected. Hardware architecture and FPGA implementation for IEEE 802.16e LDPC codes are presented. Copyright © 2011 John Wiley & Sons, Ltd.     

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network

A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22- mm² QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.     

Notice of Violation of IEEE Publication PrinciplesLDPC decoder: A cognitive radio perspective for next generation (XG) communication

With the rapid growth of multimedia communication systems during the last decade, there has been an increasing demand for improved technology for Error Correcting Code (ECO to enable the communication systems to have a reliable transmission over noisy channels. Low Density Parity Check (LDPC) codes are the best known ECC codes that can achieve data rates very close to the Shannon limit. In addition, superior error correction performance and parallelizable decoding algorithms have made LDPC codes a powerful competitor to turbo codes for reliable high speed communication applications. Recently, Cognitive Radio (CR) has been proposed as a promising technology to solve today's spectrum scarcity problem. CR promises to alleviate this spectrum shortage problem by dynamically accessing free spectrum resources. This implies that the radio has to work in multi-band, cope with various wireless channels and support various services such as voice, data and video. The basic requirement for CR is that it has a reconfigurable architecture to support multi-band and frequency adaptive operations. One of the ambitious design goals of future wireless systems, including 4G, IEEE 802.11n/802.16 standards, is to provide reliably very high data rate transmission in hostile environments: for example, around 100 Mb/s peak rate for downlink and around 30 Mb/s sum rate for uplink transmission with a low frame error rate (FER), typically less than 5 times10^-4. To ensure reliable nd error-free communication, there is a demand to consider implementing LDPC decoders in CR and frequency agile environments. In this article we discuss the design of adaptable as well as efficient LDPC decoders with low bit-error rate (BER) in low signal-to-noise ratio (SNR) channels for CR environments.     

QC LDPC码低复杂度消环算法

QC LDPC (Quasi-才yclic Low-density Parity-check)是一类半结构化的低密度奇偶校验码,其分块的矩阵结构具有超大规模集成电路实现上的便利,同时保持了优异的纠错性能. 本文针对QC LDPC码的基矩阵,提出一种移位因子的搜索方法及其改进版本。通过对基矩阵的扩展矩阵的Tanner图进行树形展开来进行环的检验,避免了传统算法中的复杂算术操作,降低了复杂度。在采用和IEEE 802.16e中码率为0.5的LDPC码方案相同的基矩阵条件下,本文的算法构造出的QC LDPC码具有更优的环长分布,同时纠错性能也有提升。      

非正则LDPC码在AWGN信道中的性能研究

简单介绍了非正则低密度奇偶校验(Low Density Parity Check,LDPC)码的结构。研究了其对数域概率译码的和积算法(Sum Product Algorithm,SPA),并对该算法的主要公式进行了推导,给出了其迭代核心部分的C语言实现伪码。对一种基于802.16e直接编码法生成的非正则LDPC码在高斯信道下进行了仿真分析,表明中短码长的非正则LDPC码已经具有优异的纠错性能。     

一种基于CS的LDPC码的抗误码方法

提出了一种基于CS(压缩感知)的LDPC码(低密度奇偶校验码)的抗误码方法。在编码端对H.264视频流中的每一个NAL(网络提取层)进行基于IEEE802.16e的LDPC编码。在解码端进行两种方法的解码,一种进行传统的LDPC解码,另一种根据压缩感知线性解码和信道码线性解码之间的联系,将基于IEEE802.16e的LDPC编解码中的校验矩阵作为压缩感知重构的测量矩阵进行压缩感知重构解码。实验结果表明,在高误码率的情况下,基于CS的LDPC码解码方法相对于传统LDPC解码方法的抗误效果更明显,为视频的抗误传输提供了新的思路。     

Efficient Multi-rate Encoder of QC-LDPC Codes Based on FPGA for WIMAX Standard

An efficient multi-rate encoder for IEEE 802.16e LDPC codes which outperforms current single rate encoders with acceptable hardware consumption and effi-cient memory consumption is proposed. This design uti-lizes the common dual-diagonal structure in parity matri-ces to avoid the inverse matrix operation which requires extensive computations. Parallel Matrix-vector multipli-cation (MVM) units, bidirectional operation and storage compression are applied to this multi-rate encoder to in-crease the encoding speed and significantly reduce the quantity of memory bits required. The proposed encoding architecture also contributes to the design of multi-rate encoders whose parity matrices are dual-diagonally struc-tured and have an Approximately lower triangular (ALT) form, such as in IEEE 802.11n and IEEE 802.22. Simu-lation results verified that the proposed encoder can effi-ciently work for all code rates specified in WIMAX stan-dard. With a maximum clock frequency of 117 MHz, the encoder achieves 3 to 10 times higher throughput than prior works. The proposed encoder is capable to switch among six rates by adjusting the input parameter and it achieves the throughput up to 1Gbps.     

一种可快速编码的QC-LDPC码构造新方法

为解决LDPC码的编码复杂度问题,使其更易于硬件实现,提出了一种可快速编码的准循环LDPC码构造方法。该方法以基于循环置换矩阵的准循环LDPC码为基础,通过适当的打孔和行置换操作,使构造码的校验矩阵具有准双对角线结构,可利用校验矩阵直接进行快速编码,有效降低了LDPC码的编码复杂度。仿真结果表明,与IEEE 802.16e中的LDPC码相比,新方法构造的LDPC码在低编码复杂度的基础上获得了更好的纠错性能。     

联合度分布优化下扩展双对角线LDPC码构造

具有低编码复杂度和低存储量的LDPC码构造算法一直是纠错编码领域的研究热点。本文根据现有对eIRA码和QC-LDPC码的研究,提出一类具有扩展双对角线的LDPC码构造算法。该码以eIRA码作为QC-LDPC码的基码,同时具有两者低编码复杂度和低存储量的特性。为了减少该结构下基矩阵扩展后引入的多个度为1的节点对码性能造成影响,本文结合该码的结构特点提出一种基于EXIT图的联合度分布全局优化算法,有效提高了码的性能。实验结果表明,相较于IEEE802.16e与IEEE802.11n标准中相同条件下的标准码,本文所构造的QC-LDPC码的性能可提高约0.1dB。      

适于分层译码算法的LDPC码构造方法

The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check (LDPC) decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts, we propose a construction algorithm of LDPC codes, to which a constraint condition is added in the Progressive Edge-Growth (PEG) algorithm. The constraint condition can guarantee that for our constructed LDPC codes, the sets of all the variable nodes connected to the consecutive layers do not share any common variable node, which can avoid the memory access conflicts. Simulation results show that the performance of our constructed LDPC codes is close to the several other LDPC codes adopted in wireless standards. Moreover, compared with the decoder for IEEE 802. 16e LDPC codes, the throughput of our LDPC decoder has large improvement, while the chip resource consumption is unchanged. Thus, our constructed LD-PC codes can be adopted in the high-speed transmission.     

Early detection of successful decoding for dual-diagonal block-based LDPC codes

Low-density parity-check (LDPC) codes [1] have attracted much attention in the last decade owing to their capacityapproaching performance. LDPC codes with a dual-diagonal blockbased structure can be encoded in linear time with lower encoder hardware complexity [2]. This class of LDPC codes is adopted by a number of standards such as wireless LAN (IEEE 802.11n) [3], wireless MAN (IEEE 802.16e, WiMAX) [4] and satellite TV (DVB-S2) [5]. LDPC codes are commonly decoded by the iterative belief-propagation (BP) algorithm. The decoder checks the parity-check equations to detect successful decoding at the end of the iteration. The Tanner graph of an irregular LDPC code consists of nodes with different degrees such that coded bits have unequal error protection [6]. Coded bits associated with higher degree nodes tend to converge to the correct answer more quickly. Hence, in order to give better protection to the transmitted data, data bits are always mapped to higher degree nodes whereas parity bits are mapped to lower degree nodes in the encoding process. The commonly used parity-check equations Hc t ? 0t will be satisfied after all the coded bits are correctly decoded. However, as discussed above, data bits converge to the correct answer much more quickly than parity bits, so some unnecessary iterations are wasted waiting for the parity bits to be decoded. In this Letter, a new set of low-complexity check equations are derived for dual-diagonal block-based LDPC codes. Early detection of successfully decoded data can be achieved by exploiting the structure and degree of distribution of the dual-diagonal parity check matrix. The decoder power, speed and complexity can be improved by adopting these equations. Simulation shows that the coding gain performance is little changed.     

误码条件下LDPC码参数的盲估计

针对非合作信号处理中LDPC码（Low-Density Parity-Check）的盲识别问题,提出了一种容错能力较强的开集识别算法.该算法通过对码字矩阵进行高斯约旦消元找到汉明重量较小的"相关列",并根据"相关列"中所包含的约束关系求得LDPC码的校验向量,然后剔除"相关列"中为"1"位置对应的错误码字.若根据高斯约旦消元求校验向量和剔除错误码字进行迭代无法得到更多校验向量,则对得到的这些校验向量进行稀疏化,再进行译码纠错.最后,综合利用校验向量的求解,错误码字的剔除,校验向量稀疏化,LDPC码译码进行迭代,实现LDPC码校验矩阵的有效重建.仿真结果表明,对于IEEE 802.16e标准中的（576,288）LDPC码,在误比特率为0.0022时,本文算法仍可以达到较好的识别效果.     

Performance analysis of channel estimation for LDPC-coded OFDM system in multipath fading channel

In this paper, the channel estimation techniques for Orthogonal Frequency Division Multiplexing （OFDM） systems based on pilot arrangement are studied and we apply Low Density Parity Check （LDPC） codes to the system of IEEE 802.16a with OFDM modulation. First investigated is the influence of channel cstimation schemes on LDPC-code based OFDM system in static and multipath fading channels. According to the different propagation environments in 802.16a system, a dynamic channel estimation scheme is proposed. A good irregular LDPC code is designed with code rate of 1/2 and code length of 1200. Simulation results show that the performance of LDPC coded OFDM system proposed in this paper is better than that of the convolution Turbo coded OFDM system proposed in IEEE standard 802.16a.     

Configurable LDPC Decoder Architectures for Regular and Irregular Codes

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3,6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths ??648,1296,1944-bits and code rates-1/2,2/3,3/4,5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.     

High coded data rate and multicodeword WiMAX LDPC decoding on Cell/BE

A novel, flexible and scalable parallel LDPC decoding approach for the WiMAX wireless broadband standard (IEEE 802.16e) in the multicore Cell broadband engine architecture is proposed. A multicodeword LDPC decoder performing the simultaneous decoding of 96 codewords is presented. The coded data rate achieved a range of 72? 80 Mbit/s, which compares well with VLSI-based decoders and is superior to the maximum coded data rate required by theWiMAX standard performing in worst case conditions. The 8-bit precision arithmetic adopted shows additional advantages over traditional 6-bit precision dedicated VLSI-based solutions, allowing better error floors and BER performance.     

LDPC码在802.16a OFDM系统 衰落信道中的性能分析

本文通过对802.16a OFDM系统信道的分析,权衡估计的性能和算法复杂度两个因素,针对不同的传输环境,提出了动态的OFDM信道估计方案.另外我们找到了一组优秀的非正则LDPC码,将其应用于IEEE 802.16a OFDM环境中,仿真验证了它们在SUI-3和SUI-5多径衰落信道环境下具有良好的性能,并和协议中提出的卷积Turbo码进行了比较,结果证明在相同条件下,本文的LDPC码可以取得比协议提出的卷积Turbo码更优越的性能,具有更好的抗多径衰落的能力.     

LDPC码在802.16a协议中的应用

基于LDPC码的优越性能,找出一组优秀的非正则LDPC码应用于IEEE802．16a OFDM环境中,并对其性能进行仿真。仿真结果表明,LDPC码在衰落信道下具有良好的纠错能力,适用于WMAN等采用OFDM的无线通信系统。