A CMOS frequency synthesizer with an injection-locked frequencydivider for a 5-GHz wireless LAN receiver

A fully integrated 5-GHz phase-locked loop (PLL) based frequency synthesizer is designed in a 0.24 μm CMOS technology. The power consumption of the synthesizer is significantly reduced by using a tracking injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. On-chip spiral inductors with patterned ground shields are also optimized to reduce the VCO and ILFD power consumption and to maximize the locking range of the ILFD. The synthesizer consumes 25 mW of power of which only 3.8 mW is consumed by the VCO and the ILFD combined. The PLL has a bandwidth of 280 kHz and a phase noise of -101 dBc/Hz at 1 MHz offset frequency. The spurious sidebands at the center of adjacent channels are less than -54 dBc     

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.     

带有自适应频率校准单元的26~41 GHz锁相环

采用45 nm SOI CMOS工艺,设计了一种带有自适应频率校准单元的26~41 GHz 锁相环。该锁相环包括输入缓冲器、鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、高速时钟选通器、分频器和频率数字校准单元。采用了基于双LC-VCO的整数分频锁相环,使用了自适应频率选择的数字校准算法,使得锁相环能在不同参考时钟下自适应地调整工作频率范围。仿真结果表明,该锁相环的输出频率能够连续覆盖26~41 GHz。输出频率为26 GHz时,相位噪声为-103 dBc/Hz@10 MHz,功耗为34.64 mW。输出频率为41 GHz时,相位噪声为-96 dBc/Hz@10 MHz,功耗为35.44 mW。     

A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS

A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with eight different output frequencies have been implemented in a 0.13-mum foundry CMOS process. The synchronous divide-by-4/5 circuit uses current mode logic (CML) D-flip-flops with resistive loads to achieve 21-GHz maximum operating frequency at input power of 0 dBm. The divider is used to implement an 8-modulus prescaler consuming 6-mA current and 9-mW power. This extremely low power consumption is achieved by radically decreasing the sizes of transistors in the divider. Utilizing the prescaler, a charge-pump integer-N PLL has been demonstrated with 20-GHz output frequency. The in-band phase noise of the PLL at 60-kHz offset and out-of-band phase noise at 10-MHz offset are ~-80 dBc/Hz and -116.1 dBc/Hz, respectively. The locking range is from 20.05 to 21 GHz. The PLL consumes 15-mA current and 22.5-mW power from a 1.5-V power supply.     

A 4224 MHz low jitter phase-locked loop in 0.13-μm CMOS technology

A 4224 MHz phase-locked loop (PLL) is implemented in 0.13 μm CMOS technology. A dynamic phase frequency detector is employed to shorten the delay reset time so as to minimize the noise introduced by the charge pump. Dynamic mismatch of charge pump is considered. By balancing the switch signals of the charge pump, a good dynamic matching characteristic is achieved. A high-speed digital frequency divider with balanced input load is also designed to improve in-band phase noise performance. The 4224 MHz PLL achieves phase noises of-94 dBc/Hz and -114.4 dBc/Hz at frequency offsets of 10 kHz and 1 MHz, respectively. The integrated RMS jitter of the PLL is 0.57 ps (100 Hz to 100 MHz) and the PLL has a reference spur of-63 dB with the second order passive low pass filter.     

A 50-GHz Phase-Locked Loop in 0.13-μ m CMOS

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13-mum logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around -10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is -63.5, -72, and -99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.     

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.     

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.     

Design of high-speed, low-power frequency dividers and phase-lockedloops in deep submicron CMOS

Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 μm CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of ±320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW     

应用于60-GHz无线通信的全差分锁相环频率综合器

A 40-GHz phase-locked loop(PLL) frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator(VCO) to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector(PFD)and the charge pump(CP) are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 d Bc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.     

A 0.5-1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs

This paper describes the design of a fully integrated low phase noise CMOS phase-locked loop for mixedsignal SoCs with a wide range of operating frequencies.The design proposes a multi-regulator PLL architecture,in which every noise-sensitive block from the PLL top level is biased from a dedicated linear or shunt regulator,reducing the parasitic noise and spur coupling between different PLL building blocks.Supply-induced VCO frequency sensitivity of the PLL is less than 0.07%-f_(vco)/1%-V_(DD).The design...     

A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-${rm mu}hbox{m}$ CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of $-$ 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm $times$ 0.95 mm.      

A 14-GHz 256/257 dual-modulus prescaler with secondary feedback and its application to a monolithic CMOS 10.4-GHz phase-locked loop

A 14-GHz 256/257 dual-modulus prescaler is implemented using secondary feedback in the synchronous 4/5 divider on a 0.18-/spl mu/m foundry CMOS process. The dual-modulus scheme utilizes a 4/5 synchronous counter which adopts a traditional MOS current mode logic clocked D flip-flop. The secondary feedback paths limit signal swing to achieve high-speed operation. The maximum operating frequency of the prescaler is 14 GHz at V/sub DD/=1.8 V. Utilizing the prescaler, a 10.4-GHz monolithic phase-locked loop (PLL) is demonstrated. The voltage-controlled oscillator (VCO) operates between 9.7-10.4 GHz. The tuning range of the VCO is 690 MHz. The phase noise of the PLL and VCO at a 3-MHz offset with I/sub vco/=4.9 mA is -117 and -119 dBc/Hz, respectively. At the current consumption of I/sub vco/=8.1 mA, the phase noise is -122 and -122 dBc/Hz, respectively. The PLL output phase noise at a 50-kHz offset is -80 dBc/Hz. The PLL consumes /spl sim/31 mA at V/sub DD/=1.8 V.     

用于高能物理实验电子读出芯片的低噪声锁相环芯片设计

基于TSMC 180 nm工艺设计并流片测试了一款用于高能物理实验的电子读出系统的低噪声、低功耗锁相环芯片。该芯片主要由鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和分频器等子模块组成,在锁相环电荷泵模块中,使用共源共栅电流镜结构精准镜像电流以减小电流失配和用运放钳位电压进一步减小相位噪声。测试结果表明,该锁相环芯片在1.8 V电源电压、输入50 MHz参考时钟条件下,可稳定输出200 MHz的差分时钟信号,时钟均方根抖动为2.26 ps(0.45 mUI),相位噪声在1 MHz频偏处为-105.83 dBc/Hz。芯片整体功耗实测为23.4 mW,锁相环核心功耗为2.02 mW。     

一种超高频RFID阅读器中的双环锁相环

采用GF 130 nm CMOS工艺,设计了一种低功耗低噪声的电荷泵型双环锁相环,该锁相环可应用于符合国际及中国标准的超高频射频识别阅读器芯片。通过对双环锁相环在带宽和工作频率上的合理设置,以及对压控振荡器中变容二极管偏置电阻及电荷泵中参考杂散的理论分析和优化设计,改进了锁相环电路功耗和噪声性能。仿真结果表明,该锁相环在输出工作频率范围为840~960 MHz时,功耗为31.21 mW,在距中心频率840.125 MHz频偏100 kHz处的相位噪声为 -108.5 dBc/Hz,频偏1 MHz处的相位噪声为 -132.3 dBc/Hz。与同类锁相环相比较,本文电路在噪声和功耗方面具有一定优势。     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

Design and performance of a robust 180 nm CMOS standalone VCO and the integrated PLL

The design details of a low power/wide tuning range phase locked loop (PLL) is presented in 180 nm CMOS together with the simulated and post fabrication measured performance. The PLL has been specifically designed for applications requiring a wide tuning range (1.55–2.28 GHz) while maintaining low power consumption (18 mW) and good phase noise (−100.9 dBc/Hz at 1 MHz). The tuning range represents significant improvement over other reported PLL CMOS implementations. To illustrate the robustness of the architecture, a 90 nm CMOS design is included with a 5.8–9.45 GHz tuning range (48%), phase noise of −111.7 dBc/Hz, and power consumption of 18.6 mW. The stand alone voltage controlled oscillator (VCO) and the PLL were fabricated on a single 180 nm die providing a unique opportunity to analyze and measure both the stand alone VCO phase noise performance and the integrated PLL phase noise performance. The contributions to the PLL phase noise (phase detector, charge pump, VCO, divider, and reference source) are delineated and both the theoretical and measured PLL phase noise performance is discussed. Design tradeoffs are included such as effect of loop bandwidth on phase noise contributions.     

Fast-switching frequency synthesizer with a discriminator-aidedphase detector

A phase-locked loop (PLL) with a fast-locked discriminator-aided phase detector (DAPD) is presented. Compared with the conventional phase detector (PD), the proposed fast-locked PD reduces the PLL pull-in time and enhances the switching speed, while maintaining better noise bandwidth. The synthesizer has been implemented in a 0.35-μm CMOS process, and the output phase noise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its power consumption is 120 mW     

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop(PLL) design for low voltage(0.8 V) applications is presented.The voltage controlled oscillator(VCO) operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector(PFD),and a new feedback structure is utilized in the charge pump(CP) for ultra-low voltage applications.The divider adopts the extende...     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...