A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ...     

一种8.75-11.2 GHz适用于802.11a/b/g零中频收发机系统低噪声分数频率综合器

介绍了一种适用于802.11a/b/g零中频接收机的超宽带分数频率综合器。文章详细推导了分数频率综合器相位噪声和杂散的数学模型,并给出了降低噪声和杂散的优化方法。实验结果表明,输出频率二分频后,在4.375GHz时积分噪声低于1度（1kHz 到100MHz);参考频率33-MHz处杂散低于-60dBc。芯片基于标准0.13微米RF CMOS工艺,电路工作电压1.2V,功耗39.6mW。     

采用有限状态机控制的升降压双通路高效率电荷泵

针对诸如系统芯片中模拟和数字模块需工作在不同电源电压下的要求,提出一种可同时提供双路输出且具有多种增益模式的电荷泵,它仅利用一组开关电容阵列,根据输入电压与负载电流的变化自动为双通路选择合适的增益对,从而在提供稳定的输出电压同时使电荷泵具有较高的转换效率。专门引入增益跳变技术,改善了增益过渡的平滑性,进一步提高了转换效率。整个调制过程采用数字状态机控制,电路结构简单,响应速度快。芯片采用TSMC 0.35μm混合信号CMOS工艺设计并制造,仿真与测试结果显示设计目标均已实现,能够同时提供稳定的1.8 V和5.0 V的双路输出,动态响应迅速,转换效率比传统多增益模式电荷泵提高了10%以上。     

一种用于脉冲式超宽带接收机的低抖动，低杂散多相输出锁相环

本文提出了一种用于脉冲式超宽带接收机的低抖动,低杂散多相输出锁相环。为了同时满足低抖动、低功耗和输出多相时钟这些需求,该锁相环基于一个环形振荡器结构。为了提高多相时钟的时间精度和相位噪声性能,设计了一个改善了噪声和匹配特性的压控振荡器。在设计中,通过良好的匹配电荷泵和仔细选择环路滤波器带宽来抑制参考频率杂散。测试结果表明,当载波频率为264 MHz时,1 MHz失调频率下的相位噪声为-118.42 dBc/Hz,均方根抖动为1.53 ps,参考频率杂散为-66.81 dBc。该芯片采用0.13 µm CMOS工艺制造,1.2 V电源电压下功耗为4.23 mW,占用0.14 mm2的面积。     

A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter,low spur multiphase phase-locked loop(PLL) for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output.In this design,a noise and matching improved voltage-controlled oscillator(VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks.By good matching achieved in the charge pump and careful choice of the l...     

一种10GHz 0.13µm CMOS 低杂散低抖动锁相环

介绍了一种10 GHz低杂散、低抖动锁相环电路。利用改进的压控振荡器和具有较小延迟复位时间动态鉴频鉴相器有效降低锁相环相位噪声,同时讨论了高频分频器噪声以及电荷泵电流失配的优化方法。电路采用中芯国际0.13µm 1.2V射频CMOS工艺实现。测量结果表明,锁相环RMS抖动为757 fs (1KHz到10MHz); 在10 kHz、1 MHz频偏处的相位噪声分别为-89与-118.1dBc/Hz;参考频率杂散低于-77dBc。芯片面积0.32 mm2,功耗30.6mW。     

A 8.75-11.2-GHz,low phase noise fractional-N synthesizer for 802.11a/b/g zero-IF transceiver

An ultra broadband fractional-N frequency synthesizer for 802.11a/b/g zero-IF transceiver application is presented.The mathematical models for the behavior of the synthesizer’s spur and phase noise are analyzed,and the optimization methodology is proposed.Measurement results exhibits that the frequency synthesizer’s integrated phase noise is less than 1°(1 kHz to 100 MHz)with a 4.375 GHz carrier(after divide-by-2),and the reference frequency spur is below-60 dBc operating with a 33 MHz reference clock.The frequency synthesizer is fabricated on a standard 0.13μm RF CMOS process and consumes 39.6 mW from a 1.2 V supply voltage.     

一个应用于GSM/PCS/DCS/WCDMA收发机的带频率自校准技术的3~5 GHz低相位噪声分数分频频率综合器

本文给出了一种应用于GSM/PCS/DCS/WCDMA收发机的低相位噪声Σ-Δ分数分频频率综合器的设计。提出了一种新的环路稳定性分析方法,从而保证了锁相环路不会因为工艺、温度以及频率的偏差而导致不稳定。所设计的压控振荡器采用经过改进的数字控制电容阵列,扩展了振荡器的调谐范围,降低了相位噪声。同时,本文还采用了一种高精度的自动频率校准技术以自动选择振荡器的频带,并且提高了其相位噪声性能。芯片在SMIC 0.13 μm CMOS工艺下制造。测试结果表明,在1.2 V电源电压下,所设计的频率综合器的锁定范围达到3.05 GHz到5.17GHz,能够覆盖所要求的5个频带,并且锁定时间小于30 μs。测试得到的带内噪声在3.8GHz、2GHz和948MHz载波频率下分别为-89、-95.5和101dBc/Hz,相应的在1 MHz频偏处的带外噪声为-121、-123和-132dBc/Hz,能够满足以上提到的协议标准对相位噪声的要求。     

A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers

正A low-phase-noise S-A fractional-TV frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented.The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise.A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity.A prototype is implemented in 0.13μm CMOS technology.The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30μs,which covers all five required frequency bands.The measured in-band phase noise are -89,-95.5 and -101 dBc/Hz for 3.8 GHz,2 GHz and 948 MHz carriers,respectively, and accordingly the out-of-band phase noise are -121,-123 and -132 dBc/Hz at 1 MHz offset,which meet the phase-noise-mask requirements of the above-mentioned standards.     

一个6GHz宽带低相位噪声CMOS LC VCO

用SMIC 0.13 μm CMOS工艺实现了一个低相位噪声的6 GHz压控振荡器(VCO).在对其相位噪声分析的基础上,通过改进和优化传统的调谐单元和噪声滤波电路以及加入源极负反馈电阻实现了一个宽带、低增益、低相位噪声VCO.测试结果显示,在中心频率频偏1 MHz处的相位噪声为-119 dBc/Hz,频率调谐范围为6...