一种用于低压防护的新型闩锁免疫双向可控硅

针对传统片上静电放电(ESD)防护器件双向可控硅(DDSCR)的低维持电压特性,设计了一种内嵌多MOS管的新型DDSCR。通过多MOS管组成的旁路通路进行分流,能够增强反偏结电场,从而提高器件抗闩锁能力。基于TCAD进行仿真,模拟TLP测试结果表明,与NLVT_DDSCR相比,新型器件的触发电压基本保持不变,维持电压从3.50 V提高到5.06 V,通过拉长关键尺寸D5,可将器件维持电压进一步提高到6.02 V,适用于电源轨为5 V的低压芯片防护。     

一种高维持电压的新型闩锁免疫双向可控硅

传统DDSCR器件过低的维持电压容易造成闩锁效应。提出了一种新型DDSCR,在传统器件阳极与阴极之间加入了浮空高掺杂的N+与P+有源区,通过P+有源区复合阱内的电子,N+有源区将电流通过器件深处电阻较低SCR路径泄放的方式来解决传统器件维持电压过低的问题,提高器件抗闩锁能力。基于TCAD的仿真结果表明,与传统DDSCR相比,新型器件的维持电压从2.9 V提高到10.5 V,通过拉长关键尺寸D7,可将器件维持电压进一步提高到13.7 V。该器件适用于I/O端口存在正负两种电压的芯片防护。     

一种用于ESD保护的双向SCR特性研究

基于0.35 μm CMOS混合信号工艺,实现了一种用于ESD保护的MDDSCR器件。通过堆叠MDDSCR单元来调整维持电压,结合TLP测试结果,说明了关键尺寸和不同的衬底连接方式对器件特性的影响。堆叠DDSCR正向触发电压(Vt1)和维持电压(VH)随着堆叠器件数量的增加而线性增加,但因为存在额外寄生通路,负向Vt1和VH分别维持在20 V和6 V左右。该器件可实现6 kV以上HBM ESD保护能力,广泛应用于汽车电子、无线基站、工业控制等电源或者信号端的双向ESD保护。     

0.18μm RF CMOS双向可控硅ESD防护器件的研究(英文)

基于传统双向可控硅(DDSCR)提出了两种静电放电(ESD)保护器件,可应对正、负ESD应力从而在2个方向上对电路进行保护。传统的DDSCR通过N-well与P-well之间的雪崩击穿来触发,而提出的新器件则通过嵌入的NMOS/PMOS来改变触发机制、降低触发电压。两种改进结构均在0.18μmRFCMOS下进行流片,并使用传输线脉冲测试系统进行测试。实验数据表明,这两种新器件具有低触发电压、低漏电流(～nA),抗ESD能力均超过人体模型2kV,同时具有较高的维持电压(均超过3.3V),可保证其可靠地用于1.8V、3.3V I/O端口而避免出现闩锁问题。     

Design of novel DDSCR with embedded PNP structure for ESD protection* Xiuwen Bi (毕秀文), Hailian Liang (梁海莲), Xiaofeng Gu (顾晓峰)?, Long Huang (黄龙)

通过在常规双向可控硅器件(DDSCR)内部嵌入一个PNP结构,提出了一种新型的静电防护(ESD)器件DDSCR-PNP,以提高器件的维持电压(Vh),降低闩锁风险。首先,分析了DDSCR-PNP器件的工作机理,理论分析表明,内嵌PNP结构(PNP_2)使器件具有很好的电压箝位能力。然后,基于0.35 μm Bipolar-CMOS-DMOS工艺制造了实验器件,并利用Barth 4002传输线脉冲测试系统进行了分析。测试结果证明了DDSCR-PNP的Vh比传统DDSCR高得多,而且通过调节P阱宽度可进一步增加Vh。然而,当P阱宽度超过12 μm时,DDSCR-PNP的漏电流(IL)出现明显波动。最后,利用Sentaurus仿真分析了影响Vh和IL的原因。结果表明,横向PNP_2有助于提高Vh并降低IL,但其作用随着P阱宽度的增大而减弱,导致IL随之增大。这种新型的DDSCR-PNP器件为高压集成电路的ESD防护提供了一种有效的解决方案。     

应用于5 V电压电路的新型闩锁免疫LVTSCR

传统低压触发可控硅(LVTSCR)维持电压过低,应用于片上ESD防护时存在闩锁风险。文章提出了一种嵌入分流路径的LVTSCR。基于0.18 μm CMOS工艺,使用Sentaurus-TCAD软件模拟人体模型,对器件准静态特性进行了分析。结果表明,新型器件在保持触发电压、ESD防护性良好的情况下,有效提高了维持电压。对关键尺寸D6进行优化,该器件的维持电压提高到5.5 V以上,器件可安全应用于5 V电压电路,避免了闩锁效应。     

内嵌PMOS的高维持电压LVTSCR设计

LVTSCR器件结构相对于普通SCR具有低电压触发特性而被广泛用于集成电路的片上静电放电(ESD)防护中。但是在ESD事件来临时,其维持电压过低易发生闩锁(latch-up)效应致使器件无法正常关断。为改进LVTSCR这一缺陷,提出了一种内嵌PMOS的高维持电压LVTSCR结构,即Embedded PMOS LVTSCR(EP-LVTSCR)。该结构基于内嵌PMOS组成的分流通路抽取阱内载流子,抑制寄生晶体管PNP与NPN正反馈效应,来提高器件抗闩锁能力;通过Sentaurus TCAD仿真软件模拟0.18μm CMOS工艺,验证器件的电流电压(I-V)特性。实验结果表明,与传统LVTSCR相比较,EP-LVTSCR的维持电压从2.01 V提升至4.50 V,触发电压从8.54 V降低到7.87 V。该器件具有良好的电压钳位特性,适用于3.3 V电源电路芯片上静电防护应用。     

双向可控硅器件在片上静电防护中的应用

设计了一种用于芯片静电放电(ESD)防护的双向可控硅(DDSCR)器件.该器件具有对称性或非对称性骤回I-V特性,可以用于多种应用场合.器件的最优静电防护性能达到94 V/μm.简洁的器件结构用于输入/输出保护,对内部电路的寄生效应小,人体模型ESD测试达到耐压等级3(超过4 kV).在多电源芯片的静电防护中,双向可控硅器件可克服普通器件不能胜任的多模式静电事件的发生.首次提出了双向可控硅器件在高速多媒体接口中静电防护和反向驱动保护的应用.     

用于高压ESD保护的双向LDMOS_SCR结构

基于横向双扩散金属氧化物半导体(LDMOS)的可控硅结构(LDMOS_SCR)因其较强的单位面积电流处理能力和出色的高压特性,通常用于高压下的静电防护。通过将原本浮空的漏极N+分割为对称的P+、N+和P+结构,提出了一种基于LDMOS_SCR的双向防护器件。该器件具有低触发和高维持电压。通过降低形成在栅极区域底部的寄生双极晶体管的发射极注入效率,减少了SCR固有的正反馈增益。基于TCAD进行仿真,实验结果表明,与传统的LDMOS_DDSCR相比,新型器件的触发电压从69.6 V降到48.5 V,维持电压从14.9 V提高到17 V,证明了提出的结构与传统LDMOS_DDSCR器件相比具有出色的抗闩锁能力     

一种用于片上静电防护的新型闩锁免疫可控硅

可控硅(SCR)被广泛应用于片上静电放电(ESD)防护。由于SCR的低维持电压特性,闩锁问题一直是其应用于高压工艺ESD防护的主要问题。改进设计了一种新型SCR器件,即MOS High-holding Voltage SCR (MHVSCR)。通过对SCR寄生三极管正反馈进行抑制,并提高维持电压,实现了闩锁免疫。详细分析了MHVSCR提高SCR维持电压的可行性、工作原理以及实现步骤。基于Sentaurus TCAD的仿真结果表明:设计的器件将传统器件的SCR维持电压从2.8 V提高至15.88 V,有效实现了SCR在12 V工艺下的闩锁免疫能力。     

一种新型的高维持电压可控硅

可控硅(SCR)作为静电放电(ESD)保护器件,因具有高的鲁棒性而被广泛应用,但其维持电压很低,容易导致闩锁问题。针对高压集成电路的ESD保护,提出了一种新颖的具有高维持电压的SCR结构(HHVSCR)。通过添加一个重掺杂的N型掺杂层(NIL),减小了SCR器件自身固有的正反馈效应,从而提高了SCR的维持电压。Sentaurus TCAD仿真结果表明,与传统的SCR相比,改进的HHVSCR无需增加额外的面积就可将维持电压从1.88 V提高到11.9 V,可应用于高压集成电路的ESD防护。     

0.18μm混合信号RFCMOS工艺中新型低触发电压双向SCR静电防护器件的设计

提出了一类新型片上SCR静电放电防护器件,此类器件用于保护芯片双向抗击静电应力.比较和分析了四种双向SCR器件的触发电压.其中采用嵌入pMOS管或nMOS管的双向SCR器件结构具有可调触发电压,低漏电流(～pA)和开启速度快的骤回Ⅰ-Ⅴ特性,并且没有闭锁问题.该器件的抗ESD能力可达～94V/μm.此类新型ESD防护器件具有面积小、寄生效应小的特点.     

用于电源线间ESD保护的新型高维持电压的SCR-LDMOS器件

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD(electro-static discharge) clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.     

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process

In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits.     

Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

In order to enhance the applications of SCR devices for deep-submicron CMOS technology, a novel SCR design with "initial-on" function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special native device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25-mum CMOS process     

应用于片上ESD防护中新式直通型MOS触发SCR器件的研究

在基于0.13μm CMOS工艺制程下,为研究片上集成电路ESD保护,对新式直通型MOS触发SCR器件和传统非直通型MOS触发SCR进行了流片验证,并对该结构各类特性进行了具体研究分析。实验采用TLP(传输线脉冲)对两类器件进行测试验证,发现新式直通型MOS触发SCR结构要比传统非直通型MOS触发SCR具有更低的触发电压、更小的导通电阻、更好的开启效率以及更高的失效电流。     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologies

Robust and novel devices called high-holding low-voltage trigger silicon controlled rectifiers (HH-LVTSCRs) for electrostatic discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Comparison between complementary n- and p-type HH-LVTSCR devices shows that n-type devices perform better than p-type devices when a low holding voltage (V/sub H/) is allowed during the on-state of the ESD protection structure, but when a relatively high holding voltage is required, p-type devices perform better. Results further demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC.