CMOS反相器辐射加固电路设计

针对CMOS反相器进行了电路级的抗总剂量辐射加固设计,对采用此电路结构反相器的抗总剂量辐射性能,利用电路模拟软件Pspice进行了模拟.模拟结果显示,采用该电路结构的反相器有很好的抗辐射性能.     

新型CMOS JK触发器

该文以双反相器闩锁电路为基本存贮单元,采用开关级设计方法设计出一种新型的CMOS JK触发器。与传统设计相比,新设计具有较简单的结构、较少的元件以及较快的工作速度。     

CMOS集成电路抗闩锁策略研究

以反相器电路为例，介绍了CMOS集成电路的工艺结构；采用双端pnpn结结构模型，较为详细地分析了CMOS电路闩锁效应的形成机理；介绍了在电路版图级、工艺级和电路应用时如何采用各种有效的技术手段来避免、降低或消除闩锁的形成，这是CMOS集成电路得到广泛应用的根本保障。     

利用反相器组成廉价的开关电源

由反相器７４０６和少量阻容元件组成的开关电源如图１所示。该电路除具有一般开关电源的功能外，它还能把５Ｖ输入电压转换为１２Ｖ输出电压，以供外电路使用。从图中看出，开关电源由振荡器、功率级和误差放大器组成。图１反相器组成的开关电源振荡器由反相器ＩＣ１Ａ、...     

高可靠性标准单元库性能参数的设计研究

为了设计高可靠性标准单元库的性能参数,需要对其最基本的单元模块反相器的性能参数进行研究。平衡考虑延时特性、噪声容限和功耗等方面的因素,首先确定反相器晶体管PMOS和NMOS的宽度比,然后根据设计需要确定具体的晶体管尺寸,提出了一套完整的确定反相器最小尺寸的方案。最后搭建一组逻辑电路验证所设计的反相器在延时特性和功耗方面体现出的优势,为深亚微米和纳米级标准单元库参数设计提供一定的依据。     

碳化硅CMOS反相器的特性

建立了6H-SiC CMOS反相器的电路结构和物理模型,并利用MEDICI软件对其特性进行了模拟.研究了SiC CMOS反相器的温度特性,结果表明,室温下沟道长度为1.5μm的6H-SiC CMOS反相器的阈值电压、高电平噪声容限和低电平噪声容限分别为1.657,3.156和1.470V,且随着温度的升高而减小.     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

碳化硅CMOS反相器的特性

建立了6 H- Si C CMOS反相器的电路结构和物理模型,并利用MEDICI软件对其特性进行了模拟.研究了Si C CMOS反相器的温度特性,结果表明,室温下沟道长度为1.5 μm的6 H- Si C CMOS反相器的阈值电压、高电平噪声容限和低电平噪声容限分别为1.6 5 7,3.15 6和1.4 70 V,且随着温度的升高而减小.     

体硅衬底上的CMOS FinFET

介绍了一种制作在普通体硅上的CMOS FinFET.除了拥有和原来SOI上FinFET类似的FinFET结构,器件本身在硅衬底中还存在一个凹槽平面MOSFET,同时该器件结构与传统的CMOS工艺完全相容,并应用了自对准硅化物工艺.实验中制作了多种应用该结构的CMOS单管以及CMOS反相器、环振电路,并包括常规的多晶硅和W/TiN金属两种栅电极.分析了实际栅长为110nm的硅基CMOS FinFET的驱动电流和亚阈值特性.反相器能正常工作并且在Vd=3V下201级CMOS环振的最小延迟为146ps/门.研究结果表明在未来VLSI制作中应用该结构的可行性.     

适用于D类音频功放的PWM高速比较器设计

设计了一种应用于CMOS D类音频功率放大器的PWM高速比较器。输入级为Rail-to-Rail结构,中间级由锁存器和自偏置差分放大器组成,输出级为反相器结构。由于采用了锁存器和自偏置放大器结构,比较器可以在很短的时间内驱动大电容,满足后续电路对驱动能力的要求。基于CSMC 0.5μm CMOS工艺的BSIM3V3Spice模型,采用Hspice对PWM比较器进行仿真。结果表明,在典型模型下,比较器的电源抑制比为56dB,直流开环增益为45dB,输入共模范围(ICMR)为-0.19～4.93V,传输延时为15ns。     

一种抑制相位噪声的多通道变时延下变频全双工收发方法

相位噪声会限制全双工(FD)收发机的自干扰抑制能力,恶化有用信号解调性能,即使全双工收发机采用发射机、接收机共用本振的结构,也无法消除相位噪声的限制作用。为了降低多径自干扰(SI)分量中相位噪声的影响,该文提出一种多通道变时延下变频全双工收发方法,具体包括可以补偿相位噪声的全双工收发机设计和能够抑制残余相位噪声的自干扰抑制算法。多通道变时延下变频全双工收发机采用多条通道接收同一天线的信号,各接收本振信号为经过不同延时调整的发射本振信号,可以在下变频时补偿多径自干扰中的相位噪声。自干扰抑制算法利用不同接收信号估计相位噪声参数,进一步降低残余相位噪声的影响。此外,该文推导了这种全双工收发方法的自干扰抑制能力,并给出了其随发射功率、接收通道数量的变化关系。分析与仿真结果表明,当接收通道数量高于自干扰信道强径数量时,多通道变时延下变频全双工接收方法不受相位噪声影响。     

全数字接收机的结构及关键技术

全数字接收机是近几年提出的新的接收机结构，它采用高稳定度晶体振荡器产生本地时钟用于解调及采样，载波相差和时钟寒时误差的消除，信号的判定等全部由数字信号处理器来完成，本文介绍了全数字接收机的体系结构，并对其实现的关键技术进行详细的讨论。     

An architecture of high-performance frequency and phase synthesis

Frequency synthesis has many applications in today's commercial electronic and telecommunication system design. Some techniques exist which can be used to generate a frequency that is an integer or fractional multiple of a reference frequency. This architecture is used to generate a signal of any desired frequency in a certain range from multiple reference signals with same frequency but different phases. These reference signals may come from a voltage-controlled oscillator (VCO) which is close looped with a reference clock by a phase-lock loop (PLL). This architecture provides some unique features, superior quality, and ease of implementation. In some cases, the synthesized frequency is time-average frequency. The signal can be treated as a carrier signal frequency modulated by another signal. Various phase-shifted versions and duty cycle versions of this signal can also be generated from this architecture. This architecture also has direct application to spread spectrum clock generation     

Nonlinear Mode Analysis and Optimization of a Triple-Push Oscillator

The triple-push oscillator architecture is an attractive application of a three element coupled oscillator array for high frequency signal generation. The desired solution to combine the power at the third harmonic and reject the first and second harmonics requires a 120 $^{circ}$ phase shift among the system elements. However, depending on the coupling strength and delay between the oscillators, the phase distribution varies, giving rise to different operating modes. Harmonic balance analysis is used to trace these multiple coexisting modes and their stability is investigated using envelope transient simulation. A design methodology is presented where optimum coupling parameters guarantee the operation of the system in the desired mode. A 13.8 GHz triple push oscillator is fabricated, and the various modes are investigated verifying the analysis.      

Low phase-noise microwave oscillators with interferometric signal processing

Phase-noise spectral density of a 9-GHz oscillator has been reduced to -160 dBc/Hz at 1-kHz offset frequency, which is the lowest phase noise ever measured at microwave frequencies. This performance was achieved by frequency locking a conventional loop oscillator to a high-Q sapphire dielectric resonator operating at the elevated level of dissipated power (/spl sim/0.4 W). Principles of interferometric microwave signal processing were applied to generate the error signal for the frequency control loop. No cryogenics were used. Two almost identical oscillators were constructed to perform classical two-oscillator phase-noise measurements where one oscillator was phase locked to another. The phase locking was implemented by electronically controlling the level of microwave power dissipated in the sapphire dielectric resonator.     

A low-jitter 125-1250-MHz process-independent and ripple-poleless0.18-μm CMOS PLL based on a sample-reset loop filter

This paper describes a low-jitter phase-locked loop (PLL) implemented in a 0.18-μm CMOS process. A sample-reset loop filter architecture is used that averages the oscillator proportional control current which provides the feedforward zero over an entire update period and hence leads to a ripple-free control signal. The ripple-free control current eliminates the need for an additional filtering pole, leading to a nearly 90° phase margin which minimizes input jitter peaking and transient locking overshoot. The PLL damping factor is made insensitive to process variations by making it dependent only upon a bandgap voltage and ratios of circuit elements. This ensures tracking between the natural frequency and the stabilizing zero. The PLL has a frequency range of 125-1250 MHz, frequency resolution better than 500 kHz, and rms jitter less than 0.9% of the oscillator period     

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.     

射频MEMS封装振荡器的稳定性研究

文章介绍了一种由MEMS圆盘谐振器和低噪声反馈电路构成的射频振荡器。MEMS谐振器具备高Q值,使得振荡器表现出良好的频率稳定性和低相位噪声。采用低成本的金锡键合工艺对双端口谐振器封装后,进一步提升了频率稳定性。低噪声电路由两级放大组成,在提供足够增益的情况下,提升了相位噪声性能。之后测试得到的相位噪声分别是在1 kHz 频偏处为-96 dBc/Hz,噪底 -128 dBc/Hz 。中期稳定性和阿伦方差的测试结果分别为±4 ppm和10 ppb。这些结果均表明,该振荡器在新一代无线通信中有广阔的应用前景。     

基于相位调制等效展宽激光线宽的极低相噪光电振荡器

光电振荡器是一种采用光电结合方式的新型微波频率源,其利用光学长时储能,可以实现极低相位噪声的信号输出。文章研究了光纤中散射噪声对光电振荡器相位噪声的影响,重点介绍了基于相位调制等效展宽激光线宽,抑制布里渊散射噪声架构,通过理论公式推导以及实验验证,表明了上述架构可极大改善光电振荡器的相位噪声。实验中采用调制频率为50 MHz、调制幅度为3.1的相位调制信号对激光线宽进行等效展宽,得到在10 GHz频率下为-157.3 dBc/Hz@10 kHz的极低相位噪声信号输出。     

An Injection-Locked Frequency-Tracking Σ∆ Direct Digital Frequency Synthesizer

A bandpass (BP) sigma-delta modulator (SigmaDeltaM)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BPSigmaDeltaM, shaping quantization noise out of the signal band. The single-bit BPSigmaDeltaM is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BPSigmaDeltaM out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BPSigmaDeltaM-based synthesizer is fabricated in a 0.25-mum digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than -105 dBc/Hz at a 10-kHz offset is achieved