随机静态存储器低能中子单粒子翻转效应

 建立了中子单粒子翻转可视化分析方法,对不同特征尺寸（0.13~1.50 μm）CMOS工艺商用随机静态存储器(SRAM)器件开展了反应堆中子单粒子翻转效应的实验研究,获得了SRAM器件的裂变谱中子单粒子翻转截面随特征尺寸变化的变化趋势。研究结果表明:SRAM器件的特征尺寸越小,其对低能中子导致的单粒子翻转的敏感性越高。     

高探测效率CMOS单光子雪崩二极管器件

基于标准0.35μm CMOS工艺设计了一种单光子雪崩二极管器件.采用p+n阱型二极管结构,同时引进保护环与深n阱结构以提高单光子雪崩二极管性能;研究了扩散n阱保护环宽度对雪崩击穿特性的影响;对器件的电场分布、击穿特性、光子探测效率、频率响应等特性进行了分析.仿真结果表明:所设计的单光子雪崩二极管器件结构直径为10μm,扩散n阱保护环宽度为1μm时,雪崩击穿电压为13.2 V,3 dB带宽可达1.6 GHz;过偏压为1 V、2 V时最大探测效率分别高达52%和55%;在波长500~800 nm之间器件响应度较好,波长为680 nm时单位响应度峰值高达0.45 A/W.     

用于FED和PDP平板显示高压驱动电路的CMOS器件

在Synopsys TCAD软件环境下,结合中国科学院微电子研究所0.8μm标准CMOS工艺条件对于高压CMOS器件进行了工艺和器件模拟。由于考虑到与标准CMOS工艺的兼容性,高压CMOS器件均采用LDMOS结构;根据RESURF技术,对于器件的漂移区进行了优化。器件模拟结果表明,高压NMOS器件源漏击穿电压为220 V;阈值电压和驱动能力分别为0.8 V和1×10-4A/μm。高压PMOS器件源漏击穿电压为-135 V;阈值电压和驱动能力分别为-9.7 V和1.8×10-4A/μm。高压CMOS器件的研制可为进一步研制FED和PDP平板显示高压驱动电路奠定基础。     

SiGe BiCMOS低噪声放大器激光单粒子效应研究

随着CMOS工艺的日益成熟和SiGe外延技术水平的不断提高, SiGe BiCMOS低噪声放大器(LNA)广泛应用于空间射频收发系统的第一级模块. SiGe HBT作为SiGe BiCMOS LNA的核心器件,天然具有优异的低温特性、抗总剂量效应和抗位移损伤效应的能力,然而,其瞬态电荷收集引起的空间单粒子效应是制约其空间应用的瓶颈问题.本文基于SiGe BiCMOS工艺低噪声放大器开展了单粒子效应激光微束实验,并定位了激光单粒子效应敏感区域.实验结果表明, SiGe HBT瞬态电荷收集是引起SiGe BiCMOS LNA单粒子效应的主要原因. TCAD模拟表明,离子在CMOS区域入射时,电离径迹会越过深沟槽隔离结构,进入SiGe HBT区域产生电子空穴对并引起瞬态电荷收集. ADS电路模拟分析表明,单粒子脉冲瞬态电压在越过第1级与第2级之间的电容时,瞬态电压峰值骤降,这表明电容在传递单粒子效应产生的瞬态脉冲过程中起着重要作用.本文实验和模拟工作为SiGe BiCMOS LNA单粒子效应抗辐射设计加固提供了技术支持.     

石墨烯场效应晶体管的X射线总剂量效应

本文针对不同结构、尺寸的石墨烯场效应晶体管(graphene field effect transistors, GFET)开展了基于10 keVX射线的总剂量效应研究.结果表明,随累积剂量的增大,不同结构GFET的狄拉克电压V_Dirac和载流子迁移率μ不断退化;相比于背栅型GFET,顶栅型GFET的辐射损伤更加严重;尺寸对GFET器件的总剂量效应决定于器件结构; 200μm×200μm尺寸的顶栅型GFET损伤最严重,而背栅型GFET是50μm×50μm尺寸的器件损伤最严重.研究表明:对于顶栅型GFET,辐照过程中在栅氧层中形成的氧化物陷阱电荷的积累是V_Dirac和μ降低的主要原因.背栅型GFET不仅受到辐射在栅氧化层中产生的陷阱电荷的影响,还受到石墨烯表面的氧吸附的影响.在此基础上,结合TCAD仿真工具实现了顶栅器件氧化层中辐射产生的氧化物陷阱电荷对器件辐射响应规律的仿真.相关研究结果对于石墨烯器件的抗辐照加固研究具有重大意义.     

8T-全局曝光CMOS图像传感器单粒子翻转及损伤机理

针对卫星轨道上空间辐射环境引起的光学相机性能退化问题,采用8晶体管(8T)-全局曝光互补金属氧化物半导体(CMOS)图像传感器进行重离子辐照实验。实验结果显示,不同功能模块寄存器发生单粒子翻转,导致输出图像出现不同的异常模式,主要表现为输出图像"卡零"、若干相邻列输出异常、整幅图像"花屏"等。结合器件的不同子电路功能、工艺结构和工作原理,分析重离子入射器件微观作用过程对宏观图像异常模式的影响,深入探讨器件不同功能模块单粒子翻转的敏感性和损伤机理。研究结果可为CMOS图像传感器加固设计、单粒子地面模拟实验方法及标准和评估技术的建立提供重要参考。     

基于标准CMOS工艺的非接触式保护环单光子雪崩二极管

基于深亚微米CMOS工艺,设计了一种采用非接触式P阱保护环来抑制边缘击穿的单光子雪崩二极管结构.采用器件仿真软件Silvaco Atlas分析了保护环间距对器件的电场分布和雪崩触发概率等特性的影响,结合物理模型计算了所设计器件的暗计数概率和光子探测效率.仿真和计算结果表明,保护环间距d=0.6μm时器件性能最优,此时击穿电压为13.5V,暗电流为10-11 A.在过偏压为2.5V时,门控模式下的暗计数概率仅为0.38%,器件在400~700nm之间具有良好的光学响应,500nm时的峰值探测效率可达39%.     

采用多晶硅场板降低单光子雪崩二极管探测器暗计数

针对削弱暗计数噪声对单光子雪崩二极管(single-photon avalanche diode, SPAD)探测器的影响,本文研究了采用多晶硅场板降低SPAD器件暗计数率(dark count rate, DCR)的机理和方法.基于0.18-μm标准CMOS工艺,在一种可缩小的P+/P阱/深N阱器件结构的P+有源区和浅沟道隔离区(shallow trench isolation, STI)之间淀积了一层多晶硅场板来减小器件暗计数噪声.测试结果表明,多晶硅场板的淀积使SPAD器件的DCR降低了一个数量级,其在高温下的暗计数性能甚至优于室温下的未淀积多晶硅场板的器件.通过TCAD仿真进一步发现, SPAD器件保护环区域的峰值电场被多晶硅场板引入到STI内部,保护环区域的整体电场降低了25%;最后通过对DCR的建模计算得出,多晶硅场板削弱了具有高缺陷密度的保护环区域的电场,使缺陷相关DCR显著降低,从而有效改善了SPAD的暗计数性能.     

纳米FinFET器件的单粒子效应研究(英文)

Fin FET器件比主流CMOS技术表现出更多优势,如快速、高集成度、低功耗、多功能性和强扩展性,基于ISE TCAD,考虑迁移率、量子效应、载流子重组、辐射效应等的影响,建立了一种纳米Fin FET器件SEE的3D仿真模型。分析了工艺掺杂浓度、栅压、粒子能量、寄生电容及技术节点等对单粒子瞬态电流的影响,并探讨了其影响机制。基于此分析,找到了一些潜在的工艺加固技术,如降低源极掺杂浓度、增加漏极和衬底的掺杂浓度、减少粒子能量、降低栅压、优化寄生电容等。     

中子单粒子效应TCAD仿真

分析了核裂变与聚变情况下,典型能量的中子与半导体器件反应,所产生的次级粒子及其能谱分布。根据中子所能导致的最恶劣情况,讨论了65nm工艺尺寸下,半导体静态存储器的单粒子效应,并给出了TCAD仿真的结果。结果显示,商用6管单元难以避免中子单粒子效应的发生。双互锁存储单元(DICE)结构在高密度设计时,也由于电荷共享效应,发生了单粒子翻转。由于电荷共享效应难以用SPICE仿真的方法得到,TCAD仿真更适用于中子单粒子免疫的SRAM设计验证。最后,讨论了65nm工艺下,中子单粒子免疫的SRAM设计,指出6管单元加电容的方式,可能是更有竞争力的方案。     

高光电探测效率CMOS单光子雪崩二极管器件

基于0.18μm CMOS工艺技术,制作了单光子雪崩二极管,可对650~950nm波段的微弱光进行有效探测.该器件采用P~+/N阱结构,P~+层深度较深,以提高对长光波的光子探测效率与响应度;采用低掺杂深N阱增大耗尽层厚度,可以提高探测灵敏度;深N阱与衬底形成的PN结可有效隔离衬底,降低衬底噪声;采用P阱保护环结构以预防过早边缘击穿现象.通过理论分析确定器件的基本结构参数及工艺参数,并对器件性能进行优化设计.实验结果表明,单光子雪崩二极管的窗口直径为10μm,器件的反向击穿电压为18.4V左右.用光强为0.001 W/cm~2的光照射,650nm处达到0.495A/W的响应度峰值;在2V的过偏压下,650~950nm波段范围内光子探测效率均高于30%,随着反向偏压的适当增大,探测效率有所提升.     

Design of Two 8-Channel Optical Demultiplexers Using 2D Photonic Crystal Homogeneous Ring Resonators

ABSTRACT

Ring resonators have always been referred to as a highly flexible structure for designing optical devices. In this paper, we have designed and evaluated two 8-channel optical demultiplexers using photonic crystal ring resonators. The purpose of this study is to investigate the flexibility of this type of resonator for designing and manufacturing optical devices based on photonic crystals. To the extent that we have investigated the literature, there is no report so far on such a study. For this purpose, two structures with the same structural parameters, but only with a difference in the type of lattice constant (square or triangular) are used. Both structures have a common photonic band gap within a proper range for telecommunication applications used in wavelength-division multiplexing (WDM) systems. Both designed structures have an average crosstalk of ?26 dB. For the demultiplexer structure with a square lattice constant, the quality factor and the transmission coefficient are 3,046 and 93.7% respectively, and its channel spacing is 1.97 nm. For the structure with a triangular lattice constant, the quality factor and the transmission coefficient are 1577.7 and 94.5%, respectively and its channel spacing is equal to 4 nm. To obtain the photonic band gap of the structures, the plane wave expansion (PWE) method is used and the output spectrum of the structures is obtained using the finite-difference time-domain (FDTD) method. The good results obtained in this study is through designing and simulating optical demultiplexer structures only by creating a change in the type of lattice constant used. This undoubtedly justifies the high flexibility of ring resonators, when used in the design of optical devices, as well as their suitability for the use in WDM systems     

Guard rings: Structures,design methodology,integration, experimental results,and analysis for RF CMOS and RF mixed signal BiCMOS silicon germanium technology

This paper will first focus on the guard ring structures, design methodology, integration, experimental results and analysis. In this paper, the focus will be on test structure design issues, electrical characterization, and computer aided design (CAD) methodologies for advanced digital design, and mixed signal applications. The integration of “parameterized cell” guard ring structures concept into a Cadence™ based design methodology for the construction of electrostatic discharge (ESD) structures, I/O design, and latchup for radio frequency (RF) CMOS and Silicon Germanium technology will be discussed. The importance of the guard ring p-cell allows for evaluation of internal and external latchup, and the ability to verify the presence of the guard ring for whole chip design checking, verification and synthesis will be addressed. Additionally, this independent guard ring concept opens the door for a new methodology for RF design of primitive and hierarchical implementations.     

Millimeter-scale self-collimation in planar photonic crystals fabricated by CMOS technology

We report self-collimating demonstration in planar photonic crystals (PhCs) fabricated in silicon-on-insulator (SOI) wafers using 0.18 μm silicon complementary metal oxide semiconductor (CMOS) techniques. This process is original in the context of self-collimating PhC. Emphasis was on demonstrating self-collimation effect through the use of standard CMOS equipment and process development of an optical test chip using a high-volume manufacturing facility. The PhC were designed on 230 nm-top-Si layer using a square lattice of air-holes with 270 nm in diameter. The lattice constant of the PhC was 380 nm. The 1 mm self-collimation was observed at the wavelengths of 1620 nm.     

Impact of neutron-induced displacement damage on the single event latchup sensitivity of bulk CMOS SRAM

Since the displacement damage induced by the neutron irradiation prior has negligible impact on the performance of the bulk CMOS SRAM, we use the neutron irradiation to degrade the minority carrier lifetime in the regions responsible for latchup. With the experimental results, we discuss the impact of the neutron-induced displacement damage on the SEL sensitivity and qualitative analyze the effectiveness of this suppression approach with TCAD simulation.     

Total ionizing radiation-induced read bit-errors in toggle magnetoresistive random-access memory devices

The 1-Mb and 4-Mb commercial toggle magnetoresistive random-access memories(MRAMs) with 0.13 μm and 0.18-μm complementary metal–oxide–semiconductor(CMOS) process respectively and different magnetic tunneling junctions(MTJs) are irradiated with a Cobalt-60 gamma source. The electrical functions of devices during the irradiation and the room temperature annealing behavior are measured. Electrical failures are observed until the dose accumulates to 120-krad(Si) in 4-Mb MRAM while the 1-Mb MRAM keeps normal. Thus, the 0.13-μm process circuit exhibits better radiation tolerance than the 0.18-μm process circuit. However, a small quantity of read bit-errors randomly occurs only in 1-Mb MRAM during the irradiation while their electrical function is normal. It indicates that the store states of MTJ may be influenced by gamma radiation, although the electrical transport and magnetic properties are inherently immune to the radiation. We propose that the magnetic Compton scattering in the interaction of gamma ray with magnetic free layer may be the origin of the read bit-errors. Our results are useful for MRAM toward space application.     

载流子色散型硅基CMOS光子器件

为了实现硅基单片光电子集成器件的实用化,介绍了采用P-I-N、双极型场效应晶体管、金属氧化物半导体和PN结结构的载流子色散型硅基CMOS光子器件的发展状况和特点,并汇报了硅基CMOS光子器件的设计和制作方面的工作.利用商业的CMOS工艺线制作的器件获得了较好的结果,光调制器消光比约18 dB,1×2光开关消光比约21 dB,谐振环的消光比8～12 dB.采用CMOS技术研制硅基光子器件,将能使集成光子学的发展上一个新的台阶.     

90 nm CMOS工艺下p+深阱掺杂浓度对电荷共享的影响

基于3维TCAD器件模拟,研究了90 nm CMOS双阱工艺下p⁺深阱掺杂对电荷共享的影响. 研究结果表明:改变p⁺深阱的掺杂浓度对PMOS管之间的电荷共享的影响要远大于NMOS管;通过增加p⁺深阱的掺杂浓度可以有效抑制PMOS管之间的电荷共享. 这一结论可用于指导电荷共享的加固. 关键词： 电荷共享 单粒子效应 +深阱掺杂')" href="#">p⁺深阱掺杂 双极晶体管效应     

Trigger mechanism of PDSOI NMOS devices for ESD protection operating under elevated temperatures

Trigger characteristics of electrostatic discharge(ESD) protecting devices operating under various ambient temperatures ranging from 30℃ to 195℃ are investigated.The studied ESD protecting devices are the H-gate NMOS transistors fabricated with a 0.18-μm partially depleted silicon-on-insulator(PDSOI) technology.The measurements are conducted by using a transmission line pulse(TLP) test system.The different temperature-dependent trigger characteristics of groundedgate(GGNMOS) mode and the gate-triggered(GTNMOS) mode are analyzed in detail.The underlying physical mechanisms related to the effect of temperature on the first breakdown voltage V_(T1) investigated through the assist of technology computer-aided design(TCAD) simulation.     

Status on the development of front-end and readout electronics for large silicon trackers

Final results on a CMOS 0.18 μm front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 μm is briefly presented.