| ASIC综合后的静态验证方法的研究 |
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| 引用本文： | 舒适,唐长文,闵昊.ASIC综合后的静态验证方法的研究[J].微电子学,2004,34(1):56-59. |
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| 作者姓名： | 舒适 唐长文 闵昊 |
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| 作者单位： | 复旦大学,专用集成电路系统与设计国家重点实验室,上海,200433 |
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| 摘 要： | 介绍了基于深亚微米CMOS工艺ASIC电路设计流程中的静态验证方法。将这种验证方法与以往的劝态验证方法进行了比较，结果表明，前者比后者更加高效和准确。由此可以说明，静态验证完全可以取代劝态验证，并且静态验证比动态验证更加适合超大规模集成电路的发展趋势。
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| 关 键 词： | ASIC 静态验证方法 深亚微米CMOS工艺 电路设计 劝态验证 集成电路 |
| 文章编号： | 1004-3365(2004)01-0056-04 |
A Study on the Static Verification Methodology for Synthesized ASIC Design |
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| SHU Shi,TANG Zhang-wen,MIN Haoanghai ,P. R. China.A Study on the Static Verification Methodology for Synthesized ASIC Design[J].Microelectronics,2004,34(1):56-59. |
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| Authors: | SHU Shi TANG Zhang-wen MIN Haoanghai P R China |
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| Affiliation: | SHU Shi,TANG Zhang-wen,MIN Haoanghai 200433,P. R. China) |
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| Abstract: | A static verification methodology for circuit design-flow of ASIC's based on very deep sub-micron CMOS technology is described in the paper.A comparison of the static verification methodology with the dynamic verification methodology indicates that the former is more efficient and more accurate than the latter.It has been shown that the static verification,which is a substitute for dynamic verification,is more suitable for VLSI's. |
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| Keywords: | ASIC Circuit synthesis Static verification Static timing analysis Formal verification |
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