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Bahram Rashidi 《International Journal of Circuit Theory and Applications》2020,48(8):1227-1243
In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box−1) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes−1 are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works. 相似文献
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半导体阵列微剂量探测器前端读出电路设计 总被引:1,自引:0,他引:1
根据三维Si SOI PIN像素微剂量探测器特性参数,设计了一种基于GF chrt018IC CMOS工艺的前端读出电路。该读出电路主要包括PMOS输入的电荷灵敏前前置放大器,有源整形滤波电路,电压比较器及基准电流源等,可实现对微剂量信号的放大、滤波降噪、甄别输出等功能。仿真测试表明:能量探测范围为5~500 fC,单通道功耗约为2 mW,总噪声性能为0.05 f C+1.6×10~(-3)fC/pF。 相似文献
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The dynamic and partial reconfiguration of FPGAs enables the dynamic placement of applicatives tasks in reconfigurable zones. However, the dynamic management of the tasks impacts the communications since they are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various interconnection networks are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the OCEAN network that supports the communication constraints into the context of dynamic reconfigurations. Thanks to a generic platform allowing in situ characterizations of network performances, fair comparisons of various Networks-On-Chip can be realized. The FPGA and ASICs implementations of the OCEAN network are also discussed. 相似文献
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针对LTE上行链路离散傅里叶变换(DFT)预编码的多模式需求,提出了一种基于ASIC的 DFT硬件电路实现方案。采用基于WFTA算法的基4/2/5/3蝶形运算单元实现35种长度的DFT运算,采用二维缓存结构实现蝶形单元流水处理。在200 MHz时钟频率、SMIC 40 nm工艺条件下,硬件电路面积为0.87 mm2,功耗为12.5 mW。仿真与综合结果表明,文中设计的DFT硬件加速器具有运算速度快、存储资源占用少的优点,适合于LTE工程应用。 相似文献
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The design process of heterogeneous systems containing electro-mechanical components and electronic circuits involves expert knowledge, methods, and tools from different engineering domains. Cost-efficient research and development of such heterogeneous systems requires a systematic design flow without gaps. A contribution towards this global goal is presented in this article. A development and synthesis tool for one-dimensional accelerometer MEMS has been implemented, calculating sensor solutions and generating the models and layouts required for a hierarchical design flow in an automatic, module-based approach. Utilizing this flow, different accelerometers have been designed, manufactured, and characterized. A dedicated readout ASIC was developed to validate their dynamic behaviour. 相似文献
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Moshe Gavrielov Xilinx全球总裁兼CEO"全球经济走出低迷的过程中,Xilinx能够在ASIC领域赢得更多的市场份额。" 相似文献