New Model and Algorithm for Hardware/Software Partitioning |
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Authors: | Ji-Gang Wu Thambipillai Srikanthan Guang-Wei Zou |
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Affiliation: | (1) Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore, 639798, Singapore |
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Abstract: | This paper focuses on the algorithmic aspects for the hardware/software (HW/SW) partitioning which searches a reasonable composition
of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution
time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW
partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source
data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution.
The proposed algorithm runs in O(n ⋅ A) for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared
with the algorithm cited in the literature.
Electronic supplementary material The online version of this article (doi:) contains supplementary material, which is available to authorized users. |
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Keywords: | algorithm hardware/software partitioning dynamic programming complexity |
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