MPEG-4视频编码器象素压缩模块的VLSI结构设计

文章设计了一种基于MPEG-4的视频压缩编码器中象素压缩模块的VLSI结构。该设计采用分布算式结构——NEDA作为DCT变换的核心技术；应用基于LUT表结构使量化／反量化模块的设计简洁明了；同时对AC／DC预测模块还应用了新的存储策略，大大降低了FPGA中宝贵的存储空间。在满足处理速度和精度的要求下，利用了较少的晶体管数目和简洁的结构实现了象素压缩模块。

VLSI Architecture of Pixel-Compression Module in MPEG-4 Video Coder

This paper presents a VLSI architecture for the pixel compression module of video encoding according to the MPEG-4 standard. We adopt a new distributed arithmetic architecture, NEDA, as a fundamental technique of the DCT/IDCT transform. The LUT table based quantization and inverse quantization make significantly simplify our design. And a new storage scheme for the AC/DC prediction is assumed to reduce the precious storage space in FPGA. The result of simulation indicates that our design can meet the IEEE specification and implemented in a very economical way.