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排序方式: 共有1318条查询结果,搜索用时 15 毫秒
1.
由于航空航天活动越发复杂,深空通信和姿态控制等航空航天电子系统大量采用集成电路芯片以提高各方面性能。随着集成电路工艺节点的进一步缩小,电路受到单粒子效应而发生错误的概率越来越大。评估集成电路对单粒子翻转(Single event upset, SEU)的敏感性对航空航天的发展具有重要意义。电路规模的增加和系统功能集成度的提高给评估速度带来了严峻挑战。本文提出了一种能适用于超大规模集成电路(Very large scale integration, VLSI)的快速故障注入方法。该方法可通过脚本自动分析电路,并修改逻辑使电路具备故障注入功能。实验结果表明,该方法实现的故障注入速度可以达到纳秒级,可大幅缓解电路规模和评估时间之间的矛盾,从而满足VLSI的评估需求。  相似文献   
2.
This paper presents the use of commercial off the shelf CMOS image sensors for the acquisition of X‐ray images with high spatial resolution. The X‐ray images, with application in biology, electronic components inspection, and paleontology research, are obtained with 8‐keV photons from a Cu tube. The quantum efficiency of the detector is estimated using attenuation lengths of photons in the sensor and compared to traditional scintillator conversion layers. The spatial resolution observed with the sensor is limited by the charge redistribution produced after photon interaction with Si.  相似文献   
3.
The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) problem is a hot topic in very-large-scale integration physical design. In practice, most of the obstacles occupy the device layer and certain lower metal layers. Therefore, we can place wires on top of the obstacles. To maximize routing resources over obstacles, we propose a heuristic for constructing a rectilinear Steiner tree with slew constraints. Our algorithm adopts an extended rectilinear full Steiner tree grid as the routing graph. We mark two types of Steiner point candidates, which are used for constructing Steiner trees and refining solutions. A shortest path heuristic variant is designed for constructing Steiner trees and it takes into account slew constraint by inhibiting growth. Furthermore, we use a pre-computed strategy to avoid calculating slew rate repeatedly. Experimental results show that our algorithm maximizes routing resources over obstacles and saves routing resources outside obstacles. Compared with the conventional OARSMT algorithm, our algorithm reduces the wire length outside obstacles by as much as 18.74% and total wire length by as much as 6.03%. Our algorithm improves the latest related algorithm by approximately 2% in terms of wire length within a reasonable running time. Additionally, calculating the slew rate only accounts for approximately 15% of the total runing time.  相似文献   
4.
为应对数据通道测试中向量生成计算复杂度的日益增长,针对加法器进行研究,提出了一种基于分治策略的加法器测试向量生成技术。首先将被测加法器电路分解为并发模块和顺序模块,分别生成对应这些模块故障全覆盖的测试向量子集,再将他们的输入信号映射为被测加法器电路的基本输入,经去除冗余向量后得到完整的测试向量集。给出的实验结果表明了该技术能有效地降低加法器测试向量生成的计算量,特别对于大规模加法器电路的测试生成,其效果更佳。  相似文献   
5.
In recent years, the major focus of VLSI design has shifted from high-speed to low-power consumption. While standard CMOS-based digital design provides substantial flexibility during pre-silicon design phases, the characteristics of the gates are set by fabrication variations and environmental conditions and cannot easily be changed at runtime. The recently proposed Dual Mode Logic (DML) family provides a novel approach to provide this capability by introducing two configurable operating modes, static and dynamic, that enable fine-grained control of the power-performance tradeoff of a logic path. However, the introduction of a new topology requires the development of both a design methodology and techniques for integration in a robust design automation flow. Standard synthesis tools do not support dynamic gates, and in particular, dual-characteristic gates. Therefore, until now, DML has been limited to small, custom-made blocks and components. In this paper, we present a novel approach for the integration of DML into standard electronic design automation tools, as part of the standard digital design flow. The development of this approach and the accompanying design methodology enables DML to be used in larger designs, such as state-of-the-art, high-speed and/or low-power SoCs. We demonstrate the employment of the proposed approach in order to benefit from DML properties, and reduce the power consumption, while simultaneously improving the operating frequency of a number of test designs.  相似文献   
6.
In this paper, we have analyzed the register complexity of direct-form and transpose-form structures of FIR filter and explored the possibility of register reuse. We find that direct-form structure involves significantly less registers than the transpose-form structure, and it allows register reuse in parallel implementation. We analyze further the LUT consumption and other resources of DA-based parallel FIR filter structures, and find that the input delay unit, coefficient storage unit and partial product generation unit are also shared besides LUT words when multiple filter outputs are computed in parallel. Based on these finding, we propose a design approach, and used that to derive a DA-based architecture for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. Interestingly, the number of registers of the proposed structure does not increase proportionately with the block-size. This is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes. Theoretical comparison shows that the proposed structure for block-size 8 and filter-length 64 involves 60% more flip-flops, 6.2 times more adders, 3.5 times more AND-OR gates, and offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure for block-size 8 and filter-length 64 involves 1.8 times less area-delay product (ADP) and energy per sample (EPS) than the existing design, and it can support 8 times higher throughput. The proposed structure for block sizes 4 and 8, respectively, consumes 38% and 50% less power than the exiting structure for the same throughput rates on average for different supply voltages.  相似文献   
7.
针对传统视频图像压缩算法时延长和成本高的问题,提出一种新的无损/近无损视频压缩算法。该算法由码率控制器和熵编码器组成,其中码率控制器通过对已有信息进行分析(上下文)来确定当前宏块的可用比特数,然后根据大量实验得出的高效Huffman码表,并结合位平面编码器对残差进行编码。实验结果表明,文中提出的视频图像压缩算法能够工作在300 MHz,吞吐量最差为1.3 pixel/cycle,同时仅用一块120*720的SRAM来存储上一行像素值,因此很好地解决了时延和成本问题。  相似文献   
8.
《国际计算机数学杂志》2012,89(3-4):169-192
The Steiner problem in a hierarchical graph model, the structured graph, is defined. The problem finds applications to hierarchical global routing. Properties of minimum-cost Steiner trees in structured graphs are investigated. A “top-down” approximate solution to the Steiner problem in structured graphs, called a top-down Steiner tree, is defined, and an algorithm is given to compute such solution. The top-down Steiner tree provides also an approximate solution to the Steiner problem in graphs admitting a structured representation. The properties of such solution are discussed and some experimental results on the quality of the approximation are presented. A reduction in time complexity is demonstrated with respect to both exact and heuristic algorithms applied to such graphs.  相似文献   
9.
This paper addresses the design and VLSI implementation of MOS‐based RC networks capable of performing time‐controlled Gaussian filtering. In these networks, all the resistors are substituted one by one by a single MOS transistor biased in the ohmic region. The design of this elementary transistor is carefully realized according to the value of the ideal resistor to be emulated. For a prescribed signal range, the MOSFET in triode region delivers an interval of instantaneous resistance values. We demonstrate that, for the elementary 2‐node network, establishing the design equation at a particular point within this interval guarantees minimum error. This equation is then corroborated for networks of arbitrary size by analyzing them from a stochastic point of view. Following the design methodology proposed, the error committed by an MOS‐based grid when compared with its equivalent ideal RC network is, despite the intrinsic nonlinearities of the transistors, below 1% even under mismatch conditions of 10%. In terms of image processing, this error hardly affects the outcome, which is perceptually equivalent to that of the ideal network. These results, extracted from simulation, are verified in a prototype vision chip with QCIF resolution manufactured in the AMS 0.35µm CMOS‐OPTO process. This prototype incorporates a focal‐plane MOS‐based RC network that performs fully programmable Gaussian filtering. Copyright © 2011 John Wiley & Sons, Ltd.  相似文献   
10.
An optimized channel estimation algorithm based on a time-spread structure in OFDM low-voltage power line communication (PLC) systems is proposed to achieve a lower bit error rate (BER). This paper optimizes the best maximum multi-path delay of the linear minimum mean square error (LMMSE) algorithm in time-domain spread OFDM systems. Simulation results indicate that the BER of the improved method is lower than that of conventional LMMSE algorithm, especially when the signal-to-noise ratio (SNR) is lower than 0 dB. Both the LMMSE algorithm and the proposed algorithm are implemented and fabricated in CSMC 0.18 μm technology. This paper analyzes and compares the hardware complexity and performance of the two algorithms. Measurements indicate that the proposed channel estimator has better performance than the conventional estimator.  相似文献   
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