| 基于FPGA的H.264去块滤波系统的优化设计 |
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| 引用本文： | 欧阳剑,杜学亮.基于FPGA的H.264去块滤波系统的优化设计[J].计算机工程,2008,34(12):239-241. |
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| 作者姓名： | 欧阳剑 杜学亮 |
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| 作者单位： | 1. 中国科学技术大学软件学院,苏州,215021;中国科学技术大学苏州研究院,苏州,215021
2. 中国科学技术大学物理系,合肥,230026 |
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| 摘 要： | 提出一种H.264去块滤波系统的优化设计方法。通过合理设计流水线级数提高并行性，适当增加内部SRAM来提高系统速度和总线利用率，使用一种层次化的有限状态机设计方法，实现对数据流的精确控制并且有效降低硬件实现复杂度。基于FPGA的验证结果显示在最坏情况下滤波每个宏块平均只需220个时钟，比原有方案快10个时钟以上。
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| 关 键 词： | H.264标准 去块滤波 有限状态机 现场可编程逻辑器件(FPGA) |
| 修稿时间： | |
Optimized Design of H.264 Deblocking Filter System Based on FPGA |
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| OUYANG Jian,DU Xue-liang.Optimized Design of H.264 Deblocking Filter System Based on FPGA[J].Computer Engineering,2008,34(12):239-241. |
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| Authors: | OUYANG Jian DU Xue-liang |
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| Affiliation: | (1. School of Software Engineering, University of Science and Technology of China, Suzhou 215021; 2. Suzhou Institute for Advanced Study, University of Science and Technology of China, Suzhou 215021; 3. College of Physics, University of Science and Technology of China, Hefei 230026) |
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| Abstract: | This paper presents an optimized deblocking filter method. The design improves the speed of system and efficiency of bus via a pipeline with suitable stages, enhancing the parallelism, and using some local SRAM. The paper presents a hierarchy Finite State Machine(FSM) design method which can control the data path precisely and reduce the complexity of hardware. The Field Programmable Gate Array(FPGA) simulation displays that filtering one Macro Block(MB) only costs 220 cycles in the worst case. |
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| Keywords: | H 264 deblocking filter Finite State Machine(FSM) Field Programmable Gate Array(FPGA) |
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