| 功率MOS和IGBT器件在无嵌位电感开关条件下的动态雪崩特性研究 |
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| 引用本文： | 陆江,田晓丽,卢烁今,周宏宇,朱阳军,韩郑生.功率MOS和IGBT器件在无嵌位电感开关条件下的动态雪崩特性研究[J].半导体学报,2013,34(3):034002-5. |
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| 作者姓名： | 陆江 田晓丽 卢烁今 周宏宇 朱阳军 韩郑生 |
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| 作者单位： | Institute of Microelectronics,Chinese Academy of Sciences |
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| 摘 要： | The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.
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| 关 键 词： | UIS test parasitic bipolar transistor power MOSFETs IGBT parasitic thyristor |
| 收稿时间： | 8/21/2012 3:06:45 PM |
| 修稿时间： | 10/7/2012 6:07:33 AM |
Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions |
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| Lu Jiang,Tian Xiaoli,Lu Shuojin,Zhou Hongyu,Zhu Yangjun and Han Zhengsheng.Dynamic avalanche behavior of power MOSFETs and IGBTs under unclamped inductive switching conditions[J].Chinese Journal of Semiconductors,2013,34(3):034002-5. |
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| Authors: | Lu Jiang Tian Xiaoli Lu Shuojin Zhou Hongyu Zhu Yangjun and Han Zhengsheng |
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| Affiliation: | Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China |
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| Abstract: | The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching (UIS) conditions is measured. This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT, which occur at different current conditions. The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor, which leads to the deterioration of the avalanche reliability of power MOSFETs. However, the results of the IGBT show two different failure behaviors. At high current mode, the failure behavior is similar to the power MOSFETs situation. But at low current mode, the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result. |
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| Keywords: | UIS test parasitic bipolar transistor power MOSFETs IGBT parasitic thyristor |
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