Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Design of Feedback Shift Register of Against Power Analysis Attack

Stream ciphers based on linear feedback shift register (LFSR) are suitable for constrained environments, such as satellite communications, radio frequency identification devices tag, sensor networks and Internet of Things, due to its simple hardware structures, high speed encryption and lower power consumption. LFSR, as a cryptographic primitive, has been used to generate a maximum period sequence. Because the switching of the status bits is regular, the power consumption of the LFSR is correlated in a linear way. As a result, the power consumption characteristics of stream cipher based on LFSR are vulnerable to leaking initialization vectors under the power attacks. In this paper, a new design of LFSR against power attacks is proposed. The power consumption characteristics of LFSR can be masked by using an additional LFSR and confused by adding a new filter Boolean function and a flip-flop. The design method has been implemented easily by circuits in this new design in comparison with the others.     

高性能通用DSP寄存器扩展设计实现方法

本文提出一种高性能通用DSP扩展寄存器的设计及实现方法,该方法是我国自主研发的高性能通用DSP中实现寄存器堆扩展的一种新方法,其优点是在不影响现有指令集及指令机器码位宽的前提下,实现对处理器内部寄存器堆的成比例扩展。通过在我国自主研制DSP上的实际应用,证明了该扩展方法的有效性和实用性。     

基于SystemView的4位m序列发生器数学模型的分析及电路设计

通过对m序列的数学模型研究分析,运用System View软件进行了4级移位寄存器模型的仿真,并对4位m序列生成器电路进行了设计研究,探讨了实现m序列的生成过程。仿真表明所设计的电路合理,其结果与理论分析一致。     

一种用于逐次逼近ADC的高能效高线性度开关电容时序

提出了一种用于逐次逼近模数转换器的高能效高线性度开关电容时序。相较于典型的基于V_CM的开关原理,该开关时序可减少37%的开关能量,并具有更高的线性度。该开关时序已应用于1V,10位300kS/s的SAR ADC,并在0.18μm标准CMOS工艺下成功流片。测试结果表明,在1V电源电压下,此SAR ADC的SNDR为55.48dB,SFDR为66.98dB,功耗为2.13μW,品质因数到达14.66fJ/c-s。DNL和INL分别为0.52/-0.47 LSB和0.72/-0.79 LSB,并且与静态非线性模型一致,最大INL出现在 V_FS/4处和3V_FS/4处。     

Novel way to research nonlinear feedback shift register

In this paper,we regard the nonlinear feedback shift register（NLFSR） as a special Boolean network,and use semi-tensor product of matrices and matrix expression of logic to convert the dynamic equations of NLFSR into an equivalent algebraic equation. Based on them,we propose some novel and generalized techniques to study NLFSR. First,a general method is presented to solve an open problem of how to obtain the properties（the number of fixed points and the cycles with different lengths） of the state sequences produced by a given NLFSR,i.e.,the analysis of a given NLFSR. We then show how to construct all 2^2^n-（l-n）/2^2^n-lshortest n-stage feedback shift registers（nFSR） and at least 2^2^n-（l-n）-1/2^2^n-l-1shortest n-stage nonlinear feedback shift registers（nNLFSR） which can output a given nonperiodic/periodic sequence with length l. Besides,we propose two novel cycles joining algorithms for the construction of full-length nNLFSR. Finally,two algorithms are presented to construct 2^2^n-2-1different full-length nNLFSRs,respectively.     

INFORMATION THEORETIC APPROACH TO SECURE LSFR CIPHERS

To break a normal LFSR cipher, a cryptanalyst needs only 2n bits of corresponding plain and ciphertext, where n is the number of stages of the shift register.[l] In this paper, a method of substituting completely random characters into the ciphertext and therefore preventing the encipherment of a full 2n-length sequence (under its proper key) will be discussed. Due to the high redundancy of English, a cipher containing several completely random characters will still be readable.     

基于存储资源迭代重用的低成本寄存器重命名方法

针对超标量深流水线中物理寄存器资源冲突造成的流水线阻塞问题,提出了一种多指令共享同一物理寄存器资源的非阻塞指令发射方法。该方法可在物理寄存器资源冲突下继续分配物理寄存器,利用发射缓冲队列临时缓冲冲突的指令,增加发射流水级实际可分配的物理寄存器数量,释放发射窗口,提高物理寄存器使用的并行性。实验结果表明:相对于传统重命名方法,该方法可减少27.3%的物理寄存器资源实现传统方法相同的性能。     

M4K块移位寄存器数据读进方式的逻辑分析仪设计

采用Altera公司的Cyclone系列EP1C3T144C8作为控制芯片,QuartusⅡ为软件平台,用硬件描述语言设计了一个具有变频采样时钟和16路采样通道,基于VGA显示的逻辑分析仪.该设计方案利用FPGA内部的M4K块作为移位寄存器不断地进行读进数据的方式,提高了工作速度、性能稳定性以及分析的范围和质量.该逻辑...     

基于BU-61580设计的1553B总线板卡

BU-61580芯片是美国DDC公司生产的、用于实现微处理器到1553B总线信号转换的接口协议芯片,具有BC/RT/MT一体化设计、单电源、电磁兼容性满足军标等特点.文中介绍了基于BU-61580设计的1553B总线板卡,扩展性强、功能强大,可广泛应用于航空、通信等领域.