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《Microelectronics Journal》2015,46(11):1012-1019
This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm2 and 0.08 mm2, respectively. 相似文献
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模拟量模块采用RS485通讯网路,将分散的现场数据点的模拟量经AD变换传输到主机或由PC控制远程主站点。模拟量模块具有计量数据采集、测量数据采集、设备开关状态采集和对外逻辑控制等多项功能,主要用作各种测控终端的数据采集、控制和显示设备,适用于各行业的自动化、信息化系统。本文介绍了一种模拟量模块的应用。 相似文献
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This paper proposes a new current-mode digital modulation circuit. The proposed circuit is MOS only hence, easily integrable. It employs an Extra X Current Conveyor (EX-CCII), two MOS transistors as switches, and a two MOS transistor-based active resistor. The amplitude shift keying/phase shift keying/frequency shift keying (ASK/PSK/FSK) modulator is obtained by proper selection of carriers (IC1, IC2). This circuit provides the current output signal at high output impedance, which is favorable for cascading. Also, the circuit is employing only MOS transistors, so it can be monolithically IC implementable. The effects of non-idealities and parasitics of the active element on the circuit performance are also investigated in detail. The functionality of the proposed digital modulator is verified through the Cadence Virtuoso tool using 0.18 μm Generic Process Design Kits parameters with the ±0.9 V supply voltage. The total area of the layout is 968.75 μm2. Also, the experimental results are verified by using the IC AD-844 and IC CD4007. 相似文献
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《Microelectronics Journal》2015,46(8):758-776
This paper presents a new high frequency Regulated Cascode (RGC) amplifier with improved performance. The split-length compensation technique is used to increase both the bandwidth and output impedance, and decrease the input impedance of the conventional RGC. The bandwidth of the proposed RGC amplifier is 5.81 GHz, which is about 2.7 GHz larger than that of simple one. The improved performance of the introduced circuit is achieved with no additional passive element and DC power dissipation. In the paper, output impedance and bandwidth of the proposed circuit are derived by using small signal analysis and have also been compared with the traditional one. In addition, a wideband high performance current mirror is designed in the work as an application of the proposed RGC structure. The bandwidth extension ratio (BWER) of the modified wideband current mirror is 1.37. The proposed circuits are designed by using TSMC 0.18 µm CMOS process and BSIM3 Level 49 device model. The circuits are simulated on Spectre simulator of Cadence to validate the analytical results obtained in the paper. 相似文献
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This paper describes the characteristics of a new CAD tool that enables the creation of layout libraries of selected analog modules. This Analog Modules Generator (AMG) automatically creates multiple layout versions of two commonly used analog structures: the differential pair and arrays of series-connected or stacked devices, for the subsequent generation of layout libraries. Based on the number of devices and rows defined by the user for the layout implementation, the tool validates all possible implementations, which are later saved in a database. Additionally, an extraction process can be optionally executed over all the layout views saved in the database. The AMG generates several reports with all the characteristics of the implemented layouts, including area and parasitic components, facilitating further statistical processing. We describe the features and capabilities of the proposed AMG tool, and several test cases are presented. Results show that suitable layout implementations can be achieved by layout and circuit designers in a very reduced amount of time. 相似文献
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In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout. 相似文献