A tool for the automatic generation and analysis of regular analog layout modules

This paper describes the characteristics of a new CAD tool that enables the creation of layout libraries of selected analog modules. This Analog Modules Generator (AMG) automatically creates multiple layout versions of two commonly used analog structures: the differential pair and arrays of series-connected or stacked devices, for the subsequent generation of layout libraries. Based on the number of devices and rows defined by the user for the layout implementation, the tool validates all possible implementations, which are later saved in a database. Additionally, an extraction process can be optionally executed over all the layout views saved in the database. The AMG generates several reports with all the characteristics of the implemented layouts, including area and parasitic components, facilitating further statistical processing. We describe the features and capabilities of the proposed AMG tool, and several test cases are presented. Results show that suitable layout implementations can be achieved by layout and circuit designers in a very reduced amount of time.     

A low complexity digital unit for scalar linear interpolation and compression

A linear interpolator with compressed output and its alternative version that supports error correction are presented in this paper. The interpolation devices can be driven by an Analog/Digital Converter (ADC) that accepts as input, low frequency signals, like sensor values. The proposed interpolation methods can correct ADC linearity errors and increase the dynamic resolution of an ADC or they can reconstruct a signal from fewer samples in non-uniform distance. If the input signal is partially exponential or logarithmic then, specific correction rules can be employed to achieve a lower signal quantization error. These rules are based on simple operations like shifts and comparisons and thus, they can be implemented using low complexity hardware. Spline, Linear, Quadratic interpolation, popular compression tools and reference signals are used to evaluate the experimental results. The proposed architecture is scalar since multiple interpolators can be connected in series. A 3-stage interpolator with 9-bit input and 12-bit typical output resolution was tested with sinusoidal input. The Signal to Noise and Distortion Ratio (SNDR) of the ADC that has been used was increased up to the double. The proposed method was also tested using a pressure sensor, an acoustic signal and image reconstruction leading to Mean Square Error (MSE) that is up to 10 times lower. The achieved compression ratio, ranges between 11% and 76%. The implementation complexity of a one stage interpolator with 9-bit input resolution requires 583 Logic Elements (LE) i.e., less than 3% of the LEs that exist in an Altera Cyclone III EP3C25N Field Programmable Gate Array (FPGA).     

基于安卓系统的模拟智能机顶盒的设计与实现

为了解决数字广播电视收费的设定,给一些酒店、旅馆等多房间大型场所带来的成本提升问题,设计并实现了智能模拟机顶盒,该机顶盒硬件层次上对HI3716C平台进行了扩展,软件层次上用安卓自带组件播放模拟信号,实现了NDK环境搭建以及上层应用(JAVA)与底层(C语言)的无缝衔接.实验结果表明,该产品效果良好,具有广阔的应用前景及商业价值,可广泛地应用在各种多房间大型场所.     

A new wideband regulated cascode amplifier with improved performance and its application

This paper presents a new high frequency Regulated Cascode (RGC) amplifier with improved performance. The split-length compensation technique is used to increase both the bandwidth and output impedance, and decrease the input impedance of the conventional RGC. The bandwidth of the proposed RGC amplifier is 5.81 GHz, which is about 2.7 GHz larger than that of simple one. The improved performance of the introduced circuit is achieved with no additional passive element and DC power dissipation. In the paper, output impedance and bandwidth of the proposed circuit are derived by using small signal analysis and have also been compared with the traditional one. In addition, a wideband high performance current mirror is designed in the work as an application of the proposed RGC structure. The bandwidth extension ratio (BWER) of the modified wideband current mirror is 1.37. The proposed circuits are designed by using TSMC 0.18 µm CMOS process and BSIM3 Level 49 device model. The circuits are simulated on Spectre simulator of Cadence to validate the analytical results obtained in the paper.     

弱胶结砂层突涌机理及预测研究

第三纪和晚侏罗时期沉积的弱胶结粉细砂层在我国东北，西南地区有广泛的分布。以东北某矿区为例，根据我国矿山存在的井下砂层突涌的现象，利用室内模拟试验，探讨了弱胶结砂层在井下形成突水涌砂的机理，为预测，防止该类事故的发生提供理论依据。     

Analog active filter design using a multi objective genetic algorithm

The selection of the correct values for passive elements, resistors, and capacitors, is an important task in analog active filter design. The classic method of choosing passive elements is a difficult task and can lead to errors. To reduce the incidence of error and human effort evolutionary optimization techniques are used to select the values of capacitors and resistors. However, due to the single objective optimization technique, these are not well suited to optimize different filter parameters. For this reason, the performance of a multi-objective genetic algorithm named non-dominated sorting genetic algorithm II (NSGA-II) against the different single objective algorithms is evaluated. Two analog active filters: A fourth order Butterworth and a second order state variable filter with the operational amplifiers in their cores are used for testing purposes. In both cases two different objects are chosen along with eight components as variables to be optimized. The component values are compatible with the E12, E24 and E96 series using NSGA-II. The computation results are better in terms of design error and allow for better resistor and capacitor choice. To reach the same or better results the NSGA-II needs fewer generations compared with other genetic algorithms for this problem.     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

基于改进BP神经网络的模拟电路故障诊断研究

根据BP神经网络特点，提出对BP神经网络改进的方法，并以某负反馈放大器为例，采用改进后的BP网络进行故障诊断，步骤包括：故障特征向量提取、原始数据归一化处理、BP网络设计与训练。结果表明，在MATLAB7．1中运用神经网络工具箱中函数进行仿真，能有效进行故障识别、改善神经网络结构、提高故障诊断精度和速度。     

Electronically tunable MOSFET-only current-mode biquad filter

A novel current mode MOSFET-only structure with multi-input single-output (MISO) is proposed. The proposed circuit is free from passive circuit elements like resistors and capacitors and able to realize low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) filter functions with using the same circuit configuration. It is also important to note that the proposed filter has electronic tunability property. The proposed circuit is laid-out in the Cadence environment using 0.18 µm TSMC CMOS technology parameters. The layout area is only 408 μm² and the power consumption is about 0.6 mW. Furthermore, to investigate the performance of the BP filter output of the proposed MISO filter, Monte Carlo and corner analyses are also presented. It is shown that the mismatches and the process variations cause only small deviations for the BP filter configuration. Furthermore, the noise performance of the proposed filter is also investigated.     

高速模数转换器动态偏置误差检测的双谱方法

本文给出了考虑噪声和动态误差时的高速模数转换器（ＡＤＣ）的动态传输模型。提出了利用双谱分析高速ＡＤＣ动态偏置误差的方法。同时，指出双谱方法可以明显地减小ＡＤＣ噪声本底对微小偏置误差测量的影响，提高测量的灵敏度和精度。最后给出的计算机模拟测试结果表明，双谱法比功率法具有更高的检测分辨率和抗噪声能力。