The analysis and comparison of two novel kinds of focusing elements as reflectors

In this article, two novel kinds of focusing elements as reflectors are analyzed and compared. One is the grooved Fresnel zone plate reflector with continuous phase‐correcting. The other called subzone paraboloid reflector, has the profile that consists of a series of paraboloids. Their diffraction efficiencies and bandwidths are described. The two elements still preserve the advantages of Fresnel zone plates, namely, low profile, high efficiency, and simple fabrication. Two dual‐reflector antennas using the proposed focusing elements as the main reflectors are simulated and the results show that these antennas have good radiation performances. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:101–108, 2015.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

数字储频及其性能分析

文章介绍了3种宽带数字储频的基本结构，分析了宽带数字储频的一个重要指标——量化噪声，根据输出信号频谱的杂散电平比较了三种结构的优劣。     

RF磁控溅射制备钛酸锶钡BST纳米薄膜

钛酸锶钡(BST)薄膜作为一种高K介质材料在微电子和微机电系统等领域具有广阔的应用前景,人们已对BST薄膜的制备工艺技术和介电性能进行了大量的研究。BST纳米薄膜的制备工艺直接影响和决定着薄膜的介电性能(介电常数、漏电流密度、介电强度等)。对RF磁控反应溅射制备BST纳米薄膜的工艺技术进行了综述。从溅射靶的制备、溅射工艺参数的优化、热处理、薄膜组分的控制,及制备工艺对介电性能的影响等方面,对现有研究成果进行了较全面的总结。     

采用RF2607的WLAN自动增益控制设计

介绍了宽动态变化范围的新型可变增益放大器RF2607的特性、功能,给出了利用RF2607设计无线局域网(WLAN)通信中自动增益控制部分的实用电路.     

射频电缆组件组装工艺浅谈

近年来国内外射频电缆组件的发展很快,射频电缆组件的性能不断提高,对射频电缆组件组装工艺也提出了更高的要求.射频电缆组件组装过程多是手工操作,产品的一致性及性能很难控制,要求有良好的工艺保证,为此介绍了射频电缆组件组装工艺,包括电缆的裁剪及剥皮、内导体的连接、外导体的连接和电气性能的测试;探讨了在组装过程中应注意的问题,以及针对内导体焊接易出现虚焊问题进行研究.     

多晶硅衬底上的RF MEMS开关

在微机械开关与硅IC工艺设计和兼容方面进行了改进,获得了一种可与IC工艺兼容的RFMEMS微机械开关.采用介质隔离工艺技术把这种RFMEMS微机械开关制作在绝缘的多晶硅衬底上,实现了与IC工艺兼容;采用在金属膜桥的端点附近刻蚀一些孔的优化方法,降低了RFMEMS微机械开关的下拉电压.用TE2 819电容测试设备测试开关的电容,测得开关的开态电容、关态电容和致动电压分别为0 32 pF、6 pF和2 5V .用HP875 3C网络分析仪对RFMEMS微机械开关进行了RF特性测试,得出RFMEMS微机械开关在频率1 5GHz下关态的隔离度为35dB ,开态的插入损耗为2dB ,用示波器测得该开关的开关     

射频板条CO_2激光器并联谐振技术的研究

本文利用周期性网络模型计算了射频板条CO2激光器电极的纵向电压分布．探讨了并联谐振技术在板条器件中获得成功运用的原因．提出了利用并联谐振技术进一步提高电压分布均匀性的两个途径．     

Bandwidth Adaptation Algorithms for Adaptive Multimedia Services in Mobile Cellular Networks

The fluctuation of available link bandwidth in mobilecellular networks motivates the study of adaptive multimediaservices, where the bandwidth of an ongoing multimedia call can bedynamically adjusted. We analyze the diverse objectives of theadaptive multimedia framework and propose two bandwidth adaptationalgorithms (BAAs) that can satisfy these objectives. The firstalgorithm, BAA-RA, takes into consideration revenue and``anti-adaptation' where anti-adaptation means that a user feelsuncomfortable whenever the bandwidth of the user's call ischanged. This algorithm achieves near-optimal total revenue withmuch less complexity compared to an optimal BAA. The secondalgorithm, BAA-RF, considers revenue and fairness, and aims at themaximum revenue generation while satisfying the fairnessconstraint defined herein. Comprehensive simulation experimentsshow that the difference of the total revenue of BAA-RA and thatof an optimal BAA is negligible. Also, numerical results revealthat there is a conflicting relationship between anti-adaptationand fairness.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.