多功能保护与告警自动调压装置

本文叙述了作者设计并制作的具有多种告警和保护功能的３８０Ｖ交流自动调压器的控制装置。它可使调压精度提高到工作电压的士１％以内，并在自动调压器输出电压过高或过低时、或出现故障时进行告警。当出现故障或误动作时自动切断调压电动机的电源。     

气动锚杆钻机冲击频率测量仪的设计

针对气动锚杆钻机冲击频率不易测量的问题,提出了一种新型气动锚杆钻机冲击频率测量仪的设计方案。该测量仪采用压力传感器采集钻机冲击信号,采用电压比较器和单稳态触发器处理冲击信号并输入到单片机,由单片机计算出钻机冲击频率。实际应用表明,该测量仪可准确、方便地测量出钻机冲击频率。     

调节阀“三断”保位方案在焦化厂的应用

根据厂区所使用的调节阀自身具备的功能以及生产工艺需求,选择合适的（三断）保位方案,分析了所选择方案的工作原理及优、缺点及适用条件.     

A 6-bit 2 GS/s ADC in 65 nm CMOS

A 6-bit 2 GS/s ADC was implemented using a 65 nm digital CMOS technology.The design is based on a single-channel flash ADC architecture,and utilizes interpolating and averaging techniques.A two-stage CML-CMOS high-speed hybrid comparator is designed for optimal speed and power performance.The total power consumption of the converter is 52 mW and the area is 0.24 mm2.The ADC achieves 42.5 dB SFDR and5.2 bit ENOB at input frequency of 123 MHz,and at Nyquist frequency 37.67 dB SFDR and 4.9 bit ENOB.     

The experimental research of a digital sampling signal converter

The sensitivity and rise time of a transient characteristic of a digital sampling signal converter are experimentally researched. The sampling converter is built at a clocked tunnel-diode comparator.     

基于MAX5494的电子测量供电系统电路设计

在传统的电子测量供电系统电路中,主要依靠人工来控制模拟电位器,这使其存在很多局限性。为了克服这些不足,利用单片机AT89C51来控制数字电位器MAX5494,实现了测量供电系统电路的自动调节和控制,不仅大大简化了电路,而且提高了系统可靠性,从而改进了传统的电子测量供电系统电路。     

低功耗SAR ADC的高性能比较器综述

目前逐次逼近型模数转换器(SAR ADC)已经成为低功耗数模混合集成电路中模数转换器的首选架构,其中的核心模块—高性能比较器的功耗大小直接决定了SAR ADC的整体功耗。文章从低功耗SAR ADC系统出发,聚焦高性能低功耗电压域和时间域比较器的发展历程与最新研究进展,总结了通过优化SAR逻辑实现低功耗比较器的技术方法。该综述为数模混合电路设计者了解并掌握SAR ADC中高性能低功耗比较器技术提供有力参考。     

基于分段电容阵列的改进型逐次逼近型ADC

为缩短高速模数转换器(ADC)中高位(MSB)电容建立时间以及减小功耗,提出了一种基于分段式电容阵列的改进型逐次逼近型(SAR)ADC结构,通过翻转小电容阵列代替翻转大电容阵列以产生高位数字码,并利用180 nm CMOS工艺实现和验证了此ADC结构。该结构一方面可以缩短产生高位数码字过程中的转换时间,提高量化速度;另一方面其可以延长大电容的稳定时间,减小参考电压的负载。通过缩小比较器输入对管的面积以减小寄生电容带来的误差,提升高位数字码的准确度。同时,利用一次性校准技术减小比较器的失配电压。最终,采用180 nm CMOS工艺实现该10 bit SAR ADC,以验证该改进型结构。结果表明,在1.8 V电源电压、780μW功耗、有电路噪声和电容失配情况下,该改进型SAR ADC得到了58.0 dB的信噪失真比(SNDR)。     

Simulation and computation of the asymmetry of a clocked balanced tunnel-diode comparator

By means of simulation and computation, a clocked balanced tunnel-diode comparator, in which the clock signal conditioner is also a tunnel diode, is studied. Simulation and computation of the tunnel-diode asymmetry required for obtaining a minimum offset of the zero level of the compensation voltage are carried out. Simulation of the clocked balanced comparator is performed by means of the Tanner T-Spice program.     

An Extended Comparator Hypothesis Account of Superconditioning.

Three conditioned taste aversion experiments with rats investigated superconditioning. In each experiment, alternate exposures of 2 flavor compounds with a common element (i.e., AB/AS) were administered to establish an inhibitory relationship between the 2 unique elements, B and S, and prior to testing, S was paired with lithium chloride (LiCl). In Experiment 1, pairings of a neutral cue (X) with S in compound with B after the AB/AS exposures resulted in superconditioning between X and S. Extinction of the common element (A) just before the S-LiCl pairing attenuated both the inhibitory relationship between B and S (Experiment 2) and superconditioning between X and S (Experiment 3). These observations suggest that superconditioning consists of enhanced performance rather than enhanced associative acquisition. (PsycINFO Database Record (c) 2010 APA, all rights reserved)