Dual TLB structure for supporting two page sizes

A new translation lookaside buffer (TLB) structure is proposed which supports dual page sizes so as to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to the results of a comparison and analysis, a similar performance can be achieved by using fewer TLB entries compared with conventional TLBs     

An Effective Personalized Service Provision Scheme Based on Virtual Space for Ubiquitous Computing Environment

The purpose of this research is to propose an efficient management scheme for Virtual Personal World (VPW) which is a model focused on service continuity of personal world. Previous ubiquitous frameworks have been concerned with where is the user is serviced and what services can be offered in that space. However those questions above are not the most important problems anymore in VPW. We also introduce a management scheme for the real world object based on the concept of Virtual Objects (VO). As users can use some services unique way with various VOs, VPW framework creates User-Generated services automatically. It helps users to satisfy their specific personalized services. Our proposed manage scheme of user-generated service increases generation of service about seven times than a scheme without generation. Consequently, we find generated services encourage user satisfaction. We simulate the possibility that a user takes proper service which is not needed generation newly.     

A banked-promotion translation lookaside buffer system

We present a simple but high performance translation lookaside buffer (TLB) system with low power consumption for use in embedded systems. Our TLB structure supports two page sizes dynamically and selectively to achieve high performance with low hardware cost. To minimize power consumption, a banked-TLB is constructed by dividing one fully associative (FA) TLB space into two separate FA TLBs. These two structures are integrated to form a banked-promotion (BP) TLB. Promotion overcomes the unbalanced utilization of a banked-TLB by moving adjacent entries out of the primary banks into a separate super-page TLB. Simulation results show that the Energy*Delay product can be reduced by about 99.8%, 19.2%, 24.2%, and 24.4% compared with a FA TLB, a micro-TLB, a banked-TLB, and a victim-TLB respectively. Therefore, the BP TLB offers high performance with low power consumption and low hardware cost.     

An on-chip cache compression technique to reduce decompression overhead and design complexity

This research explores a compressed memory hierarchy model which can increase both the effective memory space and bandwidth of each level of memory hierarchy. It is well known that decompression time causes a critical effect to the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed memory systems. This paper proposes a selective compressed memory system (SCMS) incorporating the compressed cache architecture and its management method. To reduce or hide decompression overhead, this SCMS employs several effective techniques, including selective compression, parallel decompression and the use of a decompression buffer. In addition, fixed memory space allocation method is used to achieve efficient management of the compressed blocks. Trace-driven simulation shows that the SCMS approach can not only reduce the on-chip cache miss ratio and data traffic by about 35% and 53%, respectively, but also achieve a 20% reduction in average memory access time (AMAT) over conventional memory systems (CMS). Moreover, this approach can provide both lower memory traffic at a lower cost than CMS with some architectural enhancement. Most importantly, the SCMS is a more attractive approach for future computer systems because it offers high performance in cases of long DRAM latency and limited bus bandwidth.     

Cloud computing burst system (CCBS): for exa-scale computing system

Computational scientific applications tend to be very data I/O intensive, producing a large amount of data as the execution result. In this research, we propose a new storage system using next-generation non-volatile memory that is suitable for exa-scale computing systems. This storage system is called the Cloud Computing Burst System (CCBS) and is composed of a unified table management module, data scoring module, and CCBS storage. In particular, CCBS operates as a workload enlightened storage system using its own data scoring module. The CCBS storage architecture consists of PCM/NAND Flash arrays and a data migration engine. CCBS storage cannot only provide a scaling out feature, but also improve the overall performance of the storage system. In addition, by using new non-volatile memory array, many benefits, such as low energy consumption, density scaling, and high performance, can be achieved. We demonstrate the effectiveness of our proposed system by simulating the storage system using scientific benchmarking tool. Our data scoring algorithm can provide 7% more hit rate than other methods for CCBS. In addition, our proposed system has improved storage system speed by 1.64 times, compared with only NAND Flash conventional model.     

OpenCL-based optimization methods for utilizing forward DCT and quantization of image compression on a heterogeneous platform

Recent computer systems and handheld devices are equipped with high computing capability, such as general purpose GPUs (GPGPU) and multi-core CPUs. Utilizing such resources for computation has become a general trend, making their availability an important issue for the real-time aspect. Discrete cosine transform (DCT) and quantization are two major operations in image compression standards that require complex computations. In this paper, we develop an efficient parallel implementation of the forward DCT and quantization algorithms for JPEG image compression using Open Computing Language (OpenCL). This OpenCL-based parallel implementation utilizes a multi-core CPU and a GPGPU to perform DCT and quantization computations. We demonstrate the capability of this design via two proposed working scenarios. The proposed approach also applies certain optimization techniques to improve the kernel execution time and data movements. We developed an optimal OpenCL kernel for a particular device using device-based optimization factors, such as thread granularity, work-items mapping, workload allocation, and vector-based memory access. We evaluated the performance in a heterogeneous environment, finding that the proposed parallel implementation was able to speed up the execution time of the DCT and quantization by factors of 7.97 and 8.65, respectively, obtained from 1024 × 1024 and 2084 × 2048 image sizes in 4:4:4 format.     

Improving performance on object recognition for real-time on mobile devices

Augmented reality has been on the rise due to the proliferation of mobile devices. At the same time, object recognition has also come to the fore. In particular, many studies have focused on object recognition based on markerless matching. However, most of these studies have focused on desktop systems, which can have high performance in terms of CPU and memory, rather than investigating the use of mobile systems, which have been previously unable to provide high-performance object recognition based on markerless matching. In this paper, we propose a method that uses the OpenCV mobile library to improve real-time object recognition performance on mobile systems. First, we investigate the original object recognition algorithm to identify performance bottlenecks. Second, we optimize the algorithm by analyzing each module and applying appropriate code enhancements. Last, we change the operational structure of the algorithm to improve its performance, changing the execution frequency of the object recognition task from every frame to every four frames for real-time operation. During the three frames in which the original method is not executed, the object is instead recognized using the mobile devices accelerometer. We carry out experiments to reveal how much each aspect of our method improves the overall object recognition performance; overall, experimental performance improves by approximately 800 %, with a corresponding reduction of approximately 1 % in object recognition accuracy. Therefore, the proposed technique can be used to significantly improve the performance of object recognition based on markerless matching on mobile systems for real-time operation.