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用FPGA加速深度学习算法的训练过程通常需要较长的开发周期和丰富的硬件设计经验.为了应对这一挑战,设计了一种基于自适应模板技术的深度学习算法训练加速框架,在应用规模、并行调度策略、资源使用和功能扩展上进行了深入的研究并提出了相应的优化策略.采用CPU-FPGA异构加速模板技术,提出了自适应的上层模型编译框架实现与不同硬件加速资源的适配.这种基于定制模板的软硬件协同设计可以很好地适配不同的FPGA芯片并支持算法的快速迭代.用图神经网络算法数据进行加速对比实验,实现了与CPU相比7~41倍的速度提升.  相似文献   
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Semiconductor technology continues advancing,while global on-chip interconnects do not scale with the same pace as transistors,which has become the major bottleneck for performance and integration of future giga-scale ICs.Threedimensional(3D) integration has been proposed to sustain Moore’s law by incorporating through-silicon vias(TSVs) to integrate different circuit modules in the vertical direction,which is believed to be one of the most promising techniques to tackle the interconnect scaling problem.Due to its unique characteristics,there are many research opportunities,and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-onChips(SoCs).Firstly,we use existing 2D SoCs algorithms to minimize test time for individual embedded cores.In addition,vertical interconnects,i.e.,TSVs that are used to construct the test wrapper should be taken into consideration as well.This is because TSVs typically employ bonding pads to tackle the misalignment problem,and they will occupy significant planar chip area,which may result in routing congestion.In this paper,we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively.It is composed of two steps,i.e.,scan chain allocation and functional input/output insertion,both of which can reduce TSV count significantly.Through extensive experimental evaluations,it is shown that the test wrapper chain structure designed by our method can reduce the number of test TSVs dramatically,i.e.,as much as 60.5% reductions in comparison with the random method and 26% in comparison with the intuitive method.  相似文献   
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