Generalized formulation of yield, variability, minimax and Taguchi circuit optimization problems

A generalized formulation of several circuit design problems, such as manufacturing yield optimization, circuit performance variability minimization, deterministic and statistical minimax design, Income Index maximization, Taguchi approach, etc., is developed. Several other “intermediate” problems can be defined in a sense similar to the one used in Zadeh's fuzzy set theory. A specific problem is identified by the selection of a generalized membership function ω(·) of the acceptability region, and a sequence of the values of the “smoothing” parameter β. Generalized gradient formulas are developed, and various possible algorithmic implementations discussed. As a result, trade-offs between different design strategies can be investigated by circuit designers, within one coherent methodology.     

Formulation of the drift reliability optimization problem

Drift Reliabilty (DR) of a system is related to that part of the overal system reliability that is concerned with the system element ageing and parameter dependence on such environmental conditions as temperature, level of radiation, humidity, etc. Its maximization during the system design phase is of great economic importance for the manufacturers of electronic products and other equipment. In this paper the DR optimization problem is mathematically formulated in the context of parametric manufacturing yield optimization, and some algorithmic aspects of its solution are discussed. It is shown that it is possible to formulate the problem in such a way that some measures of both the yield and the average time to failure (due to the system element drift) can be maximized, and different trade-off situations investigated. The existing efficient gradient based yield optimization algorithms can be used after only some relatively simple modifications of the gradient estimation formulas.     

A new analytical/iterative approach to statistical delay characterization of cmos digital combinational circuits

This paper is believed to be one of the first attempts to statistically characterize signal delays of basic CMOS digital building blocks. Analytic expressions in terms of the transistor geometries and technological process variations are provided for fast delay computations, to be used for manufacturing yield optimization, delay variability reduction and general VLSI circuit design for quality. the proposed approach is novel in several ways: (1) It is a combination of an accurate, semi-empirical MOS transistor model with the use of an efficient interpolation technique to link the non-physical model parameters to the ‘designable’ and ‘noise’ factors. (2) It uses several newly developed analytical delay formulae where possible and simple iterative solutions where direct analytical solutions do not exist. (3) the resulting hybrid analytical/iterative models are tuned, if necessary, to enhance the overall statistical accuracy. (4) Local delays are combined together for the analysis of complex combinational VLSI circuits. (5) C-code is generated for specific delay paths to further increase efficiency (improvement in analysis times by two to four orders of magnitude with respect to SPICE, with about 5%-10% accuracy). Examples of statistical delay characterization are used to illustrate the high accuracy of the proposed approach in modelling the influence of the ‘noise’ parameters on circuit delay relative to direct SPICE-based Monte Carlo analysis. the important impact of the proposed approach is that statistical evaluation and optimization of delays in much larger VLSI circuits will become possible.     

Efficient performance function interpolation scheme and its application to statistical circuit design

A concept of ‘maximally’ flat polynomial interpolation of circuit responses (or performance functions) is proposed, developed and exploited. This kind of simple approximation of circuit behaviour proves extremely useful for Monte Carlo statistical yield estimation and optimization. Application of the resulting interpolating polynomials may substantially reduce the number of actual, time-consuming circuit analyses. Results of all available circuit analyses can be utilized to construct the interpolating polynomials, even if their number is not sufficient for a full unique quadratic or higher-order interpolation. This is accomplished by selecting the maximally flat interpolation in which all higher-order-term coefficients are minimized in the least squares sense. More importantly, a low-cost updating of the interpolating polynomials is developed in order to accommodate the results of additional circuit simulations as they become available. Examples of this approximation of circuit responses as well as its application to yield estimation and optimization are shown.     

GOSSIP_DR: A generic software system for IC reliability optimization

In this paper, a generic software system called GOSSIP_DR able to perform Drift Reliability (DR) analysis and optimization is presented. The system was developed based on new drift reliability analysis and optimization methodologies proposed in [1, 2, 3, 4]. Several useful system features and functions are described. Applications in VLSI circuit design are given, in which degradations due to hot electron effects are considered.     

An iterative approach to VLSI circuit lifetime estimation

In this paper, the problem of VLSI circuit lifetime estimation is discussed. It is shown that lifetime determination is equivalent to finding the smallest zero of a continuous non-differentiable function for a specific circuit realization. An iterative multiple cubic spline approximation algorithm is proposed to determine the lifetime. Application in VLSI circuit analysis is given, in which the degradation resulting from the hot electron effects are considered. The results show that our proposed approach is efficient.     

Phase compensation on an OTA-C integrator for high-frequency continuous-time filters

A phase compensation technique for an OTA integrator is presented. A closed-form design equation is given which offers a simple way to implement the desired zero. SPIC simulation confirmed the analytical results obtained.<>     

Stochastic approximation approach to statistical circuit design

An application of an algorithm of stochastic approximation (SA) to statistical circuit design (yield optimisation) is proposed. Fast initial convergence of the algorithm, typical for all SA methods, has been practically demonstrated. The SA methods offer a theoretical background for the statistical circuit design, which has been lacking in mostly heuristic algorithms developed so far.     

Maximum income approach to yield optimisation

A new approach to yield optimisation is proposed, based on the maximisation of the expected manufacturer's income, expressed through a newly introduced yield measure called `income (or profit) yield index?. The measure takes into account the price decrease of inferior designs, and it can be maximised using the existing methods of yield optimisation with insignificant additional computational cost.     

Reliability modeling of flexible manufacturing systems

This paper presents a modeling approach for assessing the reliability of flexible manufacturing systems. FMSs are very difficult to model by analytical methods, because of their complexity. Many of their parameters, especially equipment failure and repair rates, exhibit great uncertainty. The proposed approach owes its success to an effective heuristic method called Group Method of Data Handling. The algorithm has proven very useful for modeling complex nonlinear systems with large number of parameters and little collected data. By combining it with analytical methods, models that closely predict the FMS output are produced that become valuable tools for evaluating FMSs during their design and operation.