An Externally Trimmed Integrated DC Current Regulator Insensitive to Conducted EMI

This paper introduces a new integrated dc current regulator using external resistive trimming, which presents a high degree of immunity against conducted electromagnetic interference (EMI). While classic topologies generate erratic bias currents that are totally different from the expected value once EMI is injected into the circuit, this new topology succeeds in producing the same fixed dc current, whether EMI is present or not. Extra filtering requiring small on-chip capacitors ensures that the ripple on the output current due to the interference remains at a very low value.     

Novel CMOS Schmitt trigger

A novel CMOS Schmitt trigger circuit has been realised, using only five MOS transistors. The circuit always guarantees hysteresis, even with very large process variations. The switching speed of the new Schmitt trigger is higher, compared to previously reported CMOS Schmitt triggers.     

A study of the cognitive and psychological profile in 16 children with congenital or juvenile myotonic dystrophy

Cost-effectiveness analysis for cervical cancer screening in Japan was performed to estimate the cost per life-year saved by the screening; cost-effectiveness ratio (CER). The analysis was made using a simulation model to estimate long-term cost and effectiveness of the screening programs. CER of cervical cancer screening was estimated to be US$ 40,604 which was 2.4 times more expensive than that for gastric cancer screening but was about the same as that for colorectal cancer screening. It was within the range of cost-effectiveness of other cancer screening programs financed under the Health and Medical Services Law for the Aged in Japan. We performed sensitivity analysis on the following seven estimates, the screening charge, the sensitivity and the specificity of the screening test, the frequency of carcinoma in situ (CIS) among cases detected in the screening program, the initial cost and the terminal cost for patients with invasive cancer, and the incidence rate of cervical cancer. The sensitivity analysis demonstrated that the screening charge was the most influential factor on CER. CER was fairly stable under various assumptions on the accuracy of the screening test, the frequency of carcinoma in situ (CIS), the treatment cost for patient, and the incidence of cervical cancer. CER was less sensitive to the changes in incidence, even to as low as a 50% decrease of the current figure. Then if the incidence rate becomes 85% of the current figure in 2015, CER would be US$ 48,176 and it was suggested that the cervical cancer screening would remain reasonably cost-effective until the year 2015.     

A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in0.7-μm CMOS

A dual-modulus divide-by-128/129 prescaler has been developed in a 0.7-μm CMOS technology. A new circuit technique enables the limitation of the high-speed section of the prescaler to only one divide-by-two flipflop. In that way, a dual-modulus prescaler with the same speed as an asynchronous divider can be obtained. The measured maximum input frequency of the prescaler is up to 2.65 GHz at 5 V power supply voltage. Running at a power supply of 3 V, the circuit consumes 8 mA at a minimum input frequency of 1.75 GHz     

Switched-capacitor filters driven with very low voltage clock signals

It is well known that the switches of a very low voltage (1.5V) switched-capacitor filter in a standard CMOS process must be driven with a clock signal higher than the power supply, often generated on-chip. The authors present, however, a technique to implement very low voltage switched-capacitor filters with switches driven at the same very low voltages.<>     

A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator withprescaler

The implementation of the two high-frequency building blocks for a low-phase-noise 1.8-GHz frequency-synthesizing PLL in a standard 0.7-μm CMOS process is discussed. The VCO uses on-chip bondwires, instead of spiral inductors, for low noise and low power. The design of these bondwire inductors is discussed in great detail. A general formula for the theoretical limit of the phase noise of LC-tuned oscillators is presented. The design of a special LC-tank allows a trade-off between noise and power. The realized VCO has a phase noise of -115 dBc/Hz at 200 kHz from the 1.8-GHz carrier and consumes 8 mA from a 3-V supply. The prescaler has a fixed division ratio of 128 and uses an enhanced ECL-alike high-frequency D-flipflop. Its power consumption is 28 mW     

Efficient reduction of electromagnetic interference effects in operational amplifiers

When subjected to electromagnetic interference, an operational amplifier will generate a DC offset. A thorough comparison between two approaches to reduce this offset is presented. Through mathematical deduction and simulations, it is shown that placing a lowpass filter at the input differential pair is superior to a double differential pair compensation topology     

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 m CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm².     

A Bandwidth Enhanced Transimpedance Amplifier with Improved Noise Performance

A new TIA topology with enhanced bandwidth is presented in this paper. By adding an extra capacitive feedback loop to the resistive feedback TIA, bandwidth and sensitivity are increased without sacrificing the low power consumption. It is shown that this topology is superior to the self-compensated TIA when the photodiode is integrated on the same die as the TIA. An implementation is presented that boosts the bandwidth by a factor of 9 and reduces the noise by a factor of 4.2 for a photodiode capacitance of 106 pF, the parasitic capacitance of a POF-compliant 1 mm integrated photodiode in 130 nm CMOS.     

A high-density, matched hexagonal transistor structure in standardCMOS technology for high-speed applications

In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance caused by the small area. The matching properties of this structure have been investigated, and these results have been compared with those for traditional finger-style structures. Exploiting the advantages, these transistors are very well suited for high-speed applications with a demand for both good matching and a small area, such as multibit current steering D/A converters or wireless applications. The test chips have been implemented in a standard 0.5-μm CMOS technology. No adaptations to the standard technology have been made to realize the structures