Data link control emulation: rapid prototyping for high-speednetworks

Data link control (DLC) emulation is an efficient and effective methodology for rapid-prototyping of high-speed network technologies. In a high-speed network attachment, DLC emulation replaces the original protocol stack with one that has two DLC protocols and performs all the necessary conversions between them. The lower portion of the protocol stack implements the prototyped network, while the upper portion implements the original high-speed network stack. This allows applications to take advantage of the improved characteristics of emerging network technologies without restructuring, rewriting, or making any investment in application, protocol, or system software that interfaces to the original high-speed network adapter. In this fashion, evaluation of new technologies is feasible in real environments at a low cost. We show that DLC emulation is a flexible and general technique that supports a wide range of data link control protocols, and we demonstrate its effectiveness through a case study, where an FDDI adapter is used to provide SMDS connectivity over T1 and T3 links. We show that DLC emulation achieves high performance at a significantly low development cost for an attachment to a new network technology, because frame conversion between DIC protocols can be implemented efficiently “on-the-fly” using rapid-prototyping hardware techniques     

Efficient model sharing for scalable collaborative classification

We propose a novel collaborative approach for document classification, combining the knowledge of multiple users for improved organization of data such as individual document repositories or emails. To this end, we distribute locally built classification models in a network of participating users, and combine the shared classifiers into more powerful meta models. In order to increase the propagation efficiency, we apply a method for selecting the most discriminative model components and transmitting them to other participants. In our experiments on four large standard collections for text classification we study the resulting tradeoffs between network cost and classification accuracy. The experimental results show that the proposed model propagation has negligible communication costs and substantially outperforms current approaches with respect to efficiency and classification quality.     

Open Mobile Alliance (OMA) security layer: Architecture, implementation and performance evaluation of the integrity unit

Security has become a very critical issue in the provision of mobile services. The Open Mobile Alliance (OMA) has specified a powerful security layer, the WTLS. In this paper, a VLSI architecture for the implementation of the WTLS integrity unit is proposed. The proposed architecture is reconfigurable in the sense that operates in three different modes: as Keyed-Hash Authentication Code (HMAC), as SHA-1 and MD5 hash functions, according to WTLS specifications. This multi-mode operation is achieved due to the reconfigurable applied design technique in the proposed architecture, which keeps the allocated area resources at a minimized level. The proposed architecture achieves high speed performance, due to the pipeline designed architecture. Especially, SHA-1 operation achieved throughput is equal to 1,7 Gbps, while MD5 operation mode bit rate is equal to 2,1 Gbps. The proposed architecture has been integrated by using VHDL and has been synthesized placed and routed in an FPGA device. Comparisons with related hash functions implementations have been done in terms of throughput, operating frequency, allocated area and Area-Delay product. The achieved performance of the SHA-1 operation mode is better at about 14–42 times compared with the other conventional works. In addition, MD5 performance is superior to the other works at about 6–18 times, in all of the cases. The proposed Integrity Unit is a very trustful and powerful solution for the WTLS layer. In addition, it can be integrated in security systems which are used for the implementation networks for wireless protocols, with special needs of integrity in data transmission. Nicolas Sklavos, Ph.D.: He is a Ph.D. Researcher with the Electrical and Computer Engineering Department, University of Patras, Greece. His interests include computer security, new encryption algorithms design, wireless communications and reconfigurable computing. He received an award for his Ph.D. thesis on “VLSI Designs of Wireless Communications Security Systems” from IFIP VLSI SOC 2003. He is a referee of International Journals and Conferences. He is a member of the IEEE, the Technical Chamber of Greece and the Greek Electrical Engineering Society. He has authored or co-authored up to 50 scientific articles in the areas of his research. Paris Kitsos, Ph.D.: He is currently pursuing his Ph.D. in the Department of Electrical and computer Engineering, University of Patras, Greece. He received the B.S. in Physics from the University of Patras in 1999. His research interests include VLSI design, hardware implementations of cryptography algorithms, security protocols for wireless communication systems and Galois field arithmetic implementations. He has published many technical papers in the areas of his research. Epaminondas Alexopoulos: He is a student of the Department of Electrical and Computer Engineering, University of Patras, Greece. His research includes hardware implementations, mobile computing and security. He has published papers in the areas of his research. Odysseas Koufopavlou, Ph.D.: He received the Diploma of Electrical Engineering in 1983 and the Ph.D. degree in Electrical Engineering in 1990, both from University of Patras, Greece. From 1990 to 1994 he was at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA. He is currently an Associate Professor at the Department of Electrical and Computer Engineering, University of Patras. His research interests include VLSI, low power design, VLSI crypto systems and high performance communication subsystems architecture and implementation. He has published more than 100 technical papers and received patents and inventions in these areas.     

Hardware implementation of Bluetooth security

Bluetooth can implement its security layer's key-generation mechanism and authentication in software or hardware. Software implementation usually satisfies user requirements, but in time-critical applications or processing-constrained devices, a hardware implementation is preferable.     

A policy-based management architecture for active and programmable networks

Next generation networks must be capable of supporting a multitude of service providers that exploit an environment in which services are dynamically deployed and quickly adapted over a common heterogeneous physical infrastructure, according to varying and sometimes conflicting customer requirements. In this context, network management must become more flexible in order to cope with these emerging conditions. More specifically, new management architectures must offer service providers the freedom to manage their services according to their own policies and seamlessly extend management functionality as the only way to react to the introduction of new services. Based on a new business model that describes such an environment, we propose a policy-based management architecture that is extensible and operates in an active and programmable network. This management architecture is part of a new network architecture that was developed in the FAIN European Union research and development IST project.     

Implementation of the SHA-2 Hash Family Standard Using FPGAs

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.     

FEC in optical communications - A tutorial overview on the evolution of architectures and the future prospects of outband and inband FEC for optical communications

The recent establishment of the 10/40 Gbps technology in DWDM optical links heralds a new era of bandwidth abundance, in response to an explosive growth of services provided through the Internet. Forward error correction (FEC) is one of the key-enabling elements in this long-awaited achievement. Borrowed from the wireless world, FEC was initially introduced in wavelength-division multiplex (WDM) optical-systems to combat amplified spontaneous emission (ASE), a form of noise native in optical amplifiers (OAs). These first generation FEC systems have been associated with a coding-gain of approximately 6 dB. However, as transmission rates gradually scaled towards 10 Gbps, other optical-impairments gained in significance, primarily nonlinear (NL) effects but also chromatic-dispersion (CD) and polarization mode dispersion (PMD). FEC turned out to be invaluable in mitigating these impairments as well