Nasopharyngeal perforation: an exceptional accident during digestive endoscopy]

We describe a case of systemic cytomegalovirus (CMV) infection in an ulcerative colitis patient admitted to the hospital for an acute flare-up of his colitis. He was treated with combination immunosuppressive therapy including i.v. cyclosporine and corticosteroids and PO azathioprine. Severe bilateral stabbing knee pain was the only manifestation of CMV disease, which quickly responded to adequate antiviral therapy.     

FPGA-based architecture for hardware compression/decompression of wide format images

In this article, we present a popular lossless compression/decompression algorithm, GZIP, and the study to implement it on an FPGA-based architecture, the ADM-XRC board from ALPHA DATA parallel system ltd. The algorithm is lossless, and applied to “bi-level” images of large size (A0 format). It ensures a minimum compression rate for the images we are considering. It aims to decrease storage requirements and transfer times, which are critical for wide format printing systems. In a wide format document industry, raster data are most of time processed in an uncompressed format, in order to apply processing (P) before printing (p). An example of a copy chain is composed of scanner, set of processing operations, storage, link and printer. We propose to use a compressed format as the new data-flow representation to improve the performances of the printing system. For example, the compression (C) is applied as soon as the data are produced by the scanner, and decompression (D) is performed at the last stage, before printing. The set of processing is applied to compressed images. The proposed architecture for the compressor is based on a hash table and the decompressor is based on a parallel decoder of the Huffman codes. We implemented the proposed architecture for compression and decompression algorithms on FPGA Xilinx Virtex XCV 400.     

252 km repeaterless 10 Gb/s transmission demonstration

Using a practical erbium-doped fiber postamplifier, a dual-stage optical preamplifier, a lithium niobate Mach-Zehnder external modulator and a dispersion-shifted line fiber, IM/DD repeaterless transmission over 252 km at 10 Gb/s with a wavelength-independent receiver sensitivity in the 1530-1565-nm range is achieved     

Implementation of an LVQ neural network with a variable size: algorithmic specification, architectural exploration and optimized implementation on FPGA devices

This paper presents an optimizing methodology for the implementation of a Learning Vector Quantization (LVQ) neural network in a Field Programmable Gate Array (FPGA) device. Starting from an algorithmic specification in the form of a Factorized and Conditioned Data Dependence Graph (GFCDD), we suggest a design methodology of the LVQ-dedicated architecture. This formal methodology is called AAA, “Algorithm Architecture Adequation”. Using graph transformations, it allows the generation of an optimized circuit implementation at the Register Transfer Level (RTL). It is associated to the SynDEx-IC software tool. Based on this formal methodology, we are able to explore and generate various LVQ network implementations by varying the LVQ sizes while minimizing the hardware resources and the design time. In addition, real-time constraints should be respected to ensure a reliable classification of vigilance states in humans from electroencephalographic signals (EEG). To validate our approach, the optimized LVQ implementation was tried on two types of Virtex devices.     

Theory of stimulated Raman scattering cancellation inwavelength-division-multiplexed systems via spectral inversion

By exploiting the reflection symmetry of the underlying evolution equations, we theoretically demonstrate that stimulated Raman scattering crosstalk in continuous-wave wavelength-division-multiplexed systems can be totally eliminated using spectral inversion techniques. We show that this result is always true, irrespective of the shape of the Raman gain curve or the loss/gain profile along the optical fiber system. These results are illustrated by means of relevant examples     

A Methodology to Implement Real-Time Applications onto Reconfigurable Circuits

This paper presents an extension of the AAA rapid prototyping methodology for the optimized implementation of real-time applications onto reconfigurable circuits. This extension is based on an unified model of factorized data dependence graphs as well to specify the application algorihtm, as to deduce the possible implementations onto reconfigurable hardware. This is formalized in terms of graphs transformations. This seamless transformation flow has been implemented in a CAD software tool called SynDEx-IC.     

Eliminating SRS channel depletion in massive WDM systems viaoptical filtering techniques

We demonstrate that the channel depletion due to stimulated Raman scattering in massive wavelength-division-multiplexed (WDM) systems can be eliminated using high-frequency pass filters. These filters, when inserted appropriately into the transmission link, can effectively suppress the SRS power flow from the WDM channels to lower frequency noise. Numerical simulations carried out on WDM systems indicate that the channel depletion penalties can be kept below 0.25 dB even for a total channel power of 2 W     

Repeaterless transmission with 62.9 dB power budget using a highly efficient erbium-doped fibre amplifier module

A 565 Mbit/s DPSK heterodyne transmission experiment has been demonstrated using a fibre post-amplifier. Over +12 dBm output powers were obtained in a both end pumping configuration for 35 mW total launched pump power, leading to a repeaterless link budget of 62.9 dB.<>     

Real-time H.264/AVC baseline decoder implementation on TMS320C6416

The H.264/AVC Advanced Video Coding standard (AVC) is poised to enable a wide range of applications. However, its increased complexity creates a big challenge for efficient software implementations. This work develops and optimises the H.264/AVC video decoder level two on the TMS320C6416 Digital Signal Processor (DSP) for video conference applications. In order to accelerate the decoding speed, several algorithmic optimisations have been ported to inverse entropy decoding and intra-prediction modules. The parallelism between algorithm execution and data transfers was fully exploited using Enhanced Direct Memory Access (EDMA) engine. Furthermore, based on the DSP architectural features, various core-specific optimisation techniques were adopted leading to an increase in speed by up to 70%. Intensive experimental tests prove that a real-time decoding on TMS320C6416 DSP running at 720?MHz is obtained for Common Intermediate Format resolution (CIF 352?×?288).     

Real-time dynamic tone-mapping operator on GPU

This article presents the parallel implementation on a GPU of a real-time dynamic tone-mapping operator. The operator we describe in this article is generic and may be used by any application. However, the goal of our work is to integrate this operator into the graphic rendering process of a car driving simulator; thus, we studied its real-time implementation. The tone-mapping operator outputs a low dynamic range (LDR) image keeping as much as possible the contrast and luminance of the original input high dynamic range (HDR) image. It performs the mapping between the luminances of the original scene to the output device??s display values. We address the problem of mapping HDR images to standard displays. In this case, the tone mapping compresses the luminances ratio. Several tone-mapping operators can be found in the literature as well as some parallelizations. However, they use either static or adaptations of static operators. We have adapted the dynamic operator of Irawan and parallelized it on GPU. Algorithmic optimizations have been performed, and we have explored the different strategies of repartition of the computation among the CPU and the GPU. We have chosen to implement on the GPU the changes between the color spaces and the interpolation of the histogram which are the most time-consuming steps on the CPU (1?C2?s per image 1,002?×?666). All of these optimizations lead to an increase of the processing rate and the number of HDR-quality images displayed to LDR per second. This operator has been implemented on a RISC processor Pentium 4?at 3.6?GHz and a GPU Nvidia 8800?GTX (728MB, 518GFLOPS). The execution speed has been multiplied by a factor of 15 compared to the naive implementation of the algorithm. The display rate reaches 30 images per second, which fulfills our goal for real-time video rate of 25 images per second.