Chinese Speech Recognition Model Based on Activation of the State Feedback Neural Network

IntroductionIn recentyears,speech recognition has made greatprogress.Commercial systems such as Via Voice( IBM Company) and Naturally Speaking 1 .0( Dragon System Company ) lead the field.Although the recognition ratio has greatlyimproved,many issues still need further research,such as,real- time in processing,systemcomplexity[4 6] ,very large scale integrated circuit( VLSI) implementation,etc.Among these issues,the implementation in VLSI is the most criticalchallenge for wide use of s…     

Automatic Identification of Customized Instruction Based on Multiple Attribute Decision-Making for Multi-Issue Architectures

This paper illustrates the importance of the configuration of function units and the change of an application’s critical path when using instruction set extension (ISE) with multi-issue architectures. This paper also presents an automatic identification approach for customized instruction without input/output number constraints for multi-issue architectures. The approach identifies customized instructions using multiple attribute decision-making based on the analysis of several attributes for each candidate...     

CERCIS:一种视频媒体编解码片上系统的设计实现

基于面向特定应用的可配置处理器架构及其设计方法,设计并完成了一种视频媒体编解码片上系统芯片,它具有通用数字信号处理器的柔性编程及特定目标应用时的高性能等特点。该视频编解码片上系统由编码和解码2部分组成,编码和解码部分都采用相同的媒体信号处理架构。媒体信号处理编码、解码架构中分别包含一个8发射超长指令字数字信号处理器核,还包括实现视频媒体应用的专用数据传输单元,变长编解码单元以及接口单元,可以完成H.263视频媒体编码和解码。在0.13μm工艺库下模拟验证表明,该片上系统在17MH z工作频率下可完成15帧/s QC IF图像的H.263编码,在10MH z工作频率下可完成15帧/s QC IF图像的H.263解码。     

利用后溯重调度过程优化簇间数据交互

在多簇处理器情况下,指令应用所带来的簇间数据交互问题已经成为制约处理器性能的关键问题。针对此问题提出了在一般的调度后进行一次后溯重调度优化过程,减少了簇间的数据交互量,提高了编译器关于处理器的利用率,同时减少了编译生成的指令序列运行时所消耗的功耗。实验结果表明,利用该方法进行调度,比列表调度算法簇间数据交互量减少平均44.36%,调度后的指令执行时间的平均减少量为24.93%,比UAS(unified assign and schedule)调度算法簇间数据交互量减少平均31.25%,调度后的指令执行时间的平均减少量为14.62%。     

CMOS门电路的功率与数据相关性

为了研究电路实现形式对密码芯片抗“功耗分析攻击”能力的影响,考察了CMOS门电路的交流馈通对电源电流的影响,输入组合对电路充放电网络的影响以及静态电流的数据相关性。对静态逻辑、N/P型动态逻辑和差分Domi-no逻辑的这3种信息泄漏机制进行了具体分析,并对这4种逻辑的2输入与门和或门进行了仿真。静态电路和普通动态电路不同输入变化对应的电流曲线间的最大差值都大于60μA,而差分Domino电路的所有电流曲线之差小于2μA。结果表明:采用N型Domino逻辑,并使数据输入只在时钟为高时有效,相对于其他逻辑功耗信息泄漏要小。     

面向多发射架构ASIP的定制功能单元的自动生成

现有定制功能单元生成算法既没有考虑发射架构的配置情况,也没有考虑关键路径的改变,因此在面对多发射架构处理器时,其性能提高效果有限.该文基于有向无环图,通过分析对比特定配置下备选节点对应用的多方面影响,使用逐点生长的方法,提出了一种新的面向多发射架构特定应用指令集处理器(ASIP)的定制功能单元自动生成算法.结合3种不同...     

Architecture Design of a Variable Length Instruction Set VLIW DSP

The cost of the central register file and the size of the program code limit the scalability of very long instruction word (VLIW) processors with increasing numbers of functional units. This paper presents the architectural design of a six-way VLIW digital signal processor (DSP) with clustered register files. The architecture uses a variable length instruction set and supports dynamic instruction dispatching. The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM. A compiler based on the Open64 was developed for the system. Evaluations show that the processor is suitable for high performance applications with a high code density and small program code size.     

ASIP Approach for Multimedia Applications Based on a Scalable VLIW DSP Architecture

The rapid development of multimedia techniques has increased the demands on multimedia processors.This paper presents a new design method to quickly design high performance processors for new multimedia applications.In this approach,a configurable processor based on the very long instruction-set word architecture is used as the basic core for designers to easily configure new processor cores for multimedia algorithm.Specific instructions designed for multimedia applications efficiently improve the performance of the target processor.Functions not implemented in the digital signal processor (DSP) core can be easily integrated into the target processor as user-defined hardware to increase the performance.Several examples are given based on the architecture.The results show that the processor performance is enhanced approximately 4 times on the H.263 codec and that the processor outperforms both DSPs and single instruction multiple data (SIMD) multimedia extension architectures by up to 8 times when computing the 2-D-IDCT.     

提高4752型IC输出频率的方法

着重介绍在应用 ４７５２型专用 ＳＰＷＭ集成电路时，即使不采用微机，亦能将其输出频率提高到 ４００ Ｈｚ以上。实验表明，这种方法是成功的。     

Digital 1 V 82 μW Pseudo-Two-Stage Class-AB OTA

A low power digital operational transconductance amplifier(OTA) was developed for low voltage switched capacitor applications.The OTA has a high slew rate(SR) and a large open loop gain with a differential pseudo-two-stage Class-AB structure.A fully compensated depletion mode capacitor is used in the switched capacitor common mode feedback block instead of a metal-insulator-metal(MIM) capacitor to reduce the fabrication cost.Simulations show that with a 1.0-V supply voltage and a 34-pF load at each output t...