2GS/s 6-bit 自校准快闪ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μ m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.     

单通道8bit1.4GS/s折叠内插ADC

基于0.18 μm CMOS工艺设计并实现了一种8 bit 1.4 GS/s ADC.芯片采用多级级联折叠内插结构降低集成度,片内实现了电阻失调平均和数字辅助失调校准.测试结果表明,ADC在1.4GHz采样率下,有效位达6.4bit,功耗小于480 mW.文章所提的综合校准方法能够有效提高ADC的静态和动态性能,显示出...     

6 bit 1.8GS/s模数转换器

超高速模数转换器(ADC)是软件无线电、高速数据采集和宽带数字化雷达的关健组成部分.快闪(SLASH)ADC具有最高的转换速度,是设计超高速ADC的最佳选择,但是其功耗、面积都随分辨率指数增长,且对工艺离散敏感,因此需要综合考虑各项指标来进行芯片架构优化.     

8bit 1.4GS/s模数转换器

超高速模数转换器(ADC)是软件无线电、高速数据采集和宽带数字化雷达的关键组成部分.附带校准技术的折叠内插ADC具有等同快闪(FLASH)ADC的高转换速度,是设计超高速ADC的最佳选择,但仍需综合考虑各项指标来时行校准方法设计及芯片架构优化.     

A 2-GS/s 6-bit self-calibrated flash ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μm CMOS.The calibration method based on DAC trimming improves the linearity and dynamic performance further.The peak DNL and INL are measured as 0.34 and 0.22 LSB,respectively.The SNDR and SFDR have achieved 36.5 and 45.9 dB,respectively,with 1.22 MHz input signal and 2 GS/s.The proposed ADC,including on-chip track-and-hold amplifiers and clock buffers,consumes 570 mW from a single 1...