Distributed non-negative matrix factorization with determination of the number of latent features

The Journal of Supercomputing - The holistic analysis and understanding of the latent (that is, not directly observable) variables and patterns buried in large datasets is crucial for data-driven...     

Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS

In this work, a robust, low-power, widely linear multiphase clock generation and multiplying delay-locked loop (MPCG-MDLL) architecture is realized, using a new differential charge-mode delay element circuit topology. The heart of any MPCG-MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG-MDLL, in terms of its specifications such as peak-to-peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight-phase MPCG-MDLL along with the charge-mode delay element outperforms the conventional MPCG-MDLLs that deploy delay elements such as a current-starved inverter (CSI), wide-range CSI, triply controlled delay cell, digital-controlled delay element, and the like. The eight-phase MPCG-MDLL along with the new charge-mode delay element circuit topology is implemented in 1.2-V, 65-nm CMOS technology. The performance results show that the eight-stage delay line has a delay range from 640 to 960 ps over the rail-to-rail control voltage range. The implemented MPCG-DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak-to-peak jitter of less than 60 fs for all the DLL output phases and peak-to-peak jitter of 0.54 and 1.24 ps for the synthesized 5-GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG-MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm².     

Software Defect Prediction Based Ensemble Approach

Software systems have grown significantly and in complexity. As a result of these qualities, preventing software faults is extremely difficult. Software defect prediction (SDP) can assist developers in finding potential bugs and reducing maintenance costs. When it comes to lowering software costs and assuring software quality, SDP plays a critical role in software development. As a result, automatically forecasting the number of errors in software modules is important, and it may assist developers in allocating limited resources more efficiently. Several methods for detecting and addressing such flaws at a low cost have been offered. These approaches, on the other hand, need to be significantly improved in terms of performance. Therefore in this paper, two deep learning (DL) models Multilayer preceptor (MLP) and deep neural network (DNN) are proposed. The proposed approaches combine the newly established Whale optimization algorithm (WOA) with the complementary Firefly algorithm (FA) to establish the emphasized metaheuristic search EMWS algorithm, which selects fewer but closely related representative features. To find the best-implemented classifier in terms of prediction achievement measurement factor, classifiers were applied to five PROMISE repository datasets. When compared to existing methods, the proposed technique for SDP outperforms, with 0.91% for the JM1 dataset, 0.98% accuracy for the KC2 dataset, 0.91% accuracy for the PC1 dataset, 0.93% accuracy for the MC2 dataset, and 0.92% accuracy for KC3.