应用于软件无线电的四阶可重构模拟基带滤波器

本文提出了一个应用于软件无线电的四阶可重构模拟基带滤波器。该滤波器采用有数字辅助的有源RC低通结构,可以灵活地改变滤波器的特性,比如截止频率,选择性,类型,噪声,增益和功耗。为了同时达到优化噪声和调节功耗的目的,这里采用了一种新的可配置运放结构。该芯片采用SMIC 0.13μm CMOS工艺制作。主体滤波器和频率校准电路的面积分别为1.8 × 0.8 mm2和0.48 × 0.25 mm2。测试结果表明,该滤波器可以提供巴特沃斯和切比雪夫两种响应,而且截止频率可以覆盖从280kHz 到15MHz的宽带范围,同时可调增益范围为0dB到18dB。在1.2V的电源电压下获得29dBm的IIP3。根据给定的协议,输入参考噪声密度在41 nV/Hz½ 到133 nV/Hz½之间变化,低频带和高频带模式分别消耗了5.46mW和8.74mW的功耗。     

A wideband CMOS VGLNA based on single-to-differential stage and resistive attenuator for TV tuners

A wideband CMOS variable gain low noise amplifier(VGLNA) based on a single-to-differential(S2D) stage and resistive attenuator is presented for TV tuner applications.Detailed analysis of input matching,noise figure(NF) and linearity for S2D is given.A highly linear passive resistive attenuator is proposed to provide 6 dB attenuation and input matching for each gain stage.The chip was fabricated by a 0.18μm 1P6M CMOS process, and the measurements show that the VGLNA covers a gain range over 36.4 dB and achieves a maximum gain of 21.3 dB,a minimum NF of 3.0 dB,an IIP3 of 0.9 dBm and an IIP2 of 26.3 dBm at high gain mode with a power consumption less than 10 mA from a 1.8 V supply.     

Analysis and design of a 1.8-2.7 GHz tunable 8-band TDD LTE receiver front-end

This paper describes the analysis and design of a 0.13μm CMOS tunable receiver front-end that supports 8 TDD LTE bands,covering the 1.8-2.7 GHz frequency band and supporting the 5/10/15/20 MHz bandwidth and QPSK/16QAM/64QAM modulation schemes.The novel zero-IF receiver core consists of a tunable narrowband variable gain low-noise amplifier(LNA),a current commutating passive down-conversion mixer with a 2nd order low pass trans-impedance amplifier,an LO divider,a rough gain step variable gain pre-amplifier,a tunable 4th order Chebyshev channel select active-RC low pass filter with cutoff frequency calibration circuit and a fine gain step variable gain amplifier.The LNA can be tuned by reconfiguring the output parallel LC tank to the responding frequency band,eliminating the fixed center frequency multiple LNA array for a multi-mode receiver. The large various gain range and bandwidth of the analog baseband can also be tuned by digital configuration to satisfy the specification requirement of various bandwidth and modulation schemes.The test chip is implemented in an SMIC 0.13μm 1P8M CMOS process.The full receiver achieves 4.6 dB NF,-14.5 dBm out of band IIP3, 30-94 dB gain range and consumes 54 mA with a 1.2 V power supply.     

A 4.2-5 GHz,low phase noise LC-VCO with constant bandwidth and small tuning gain

As the tuning frequency of an integrated LC-voltage controlled oscillator （LC-VCO） increases, it is difficult to co-design the active negative resistance core and the varactor to achieve wideband frequency range, low phase noise, constant bandwidth and small tuning gain together. The presented VCO solves the problem by designing a set of changeable varactor units. The whole VCO was implemented in a 0.18μm CMOS process. The measured result shows -120 dBc/Hz phase noise at 1 MHz offset. The measured tuning range is from 4.2 to 5 GHz and the tuning gain is 8-10 MHz/V. The VCO draws 4 mA from a 1.5 V supply voltage.     

一种用于900MHz射频识别（RFID）读写器芯片的1.8V CMOS直接变频接收机

设计了针对解决900MHz RFID读写器收发机芯片中本地载波干扰问题而优化的直接变频接收机,并在0.18μm 1P6M 混合信号CMOS工艺上实现验证. 设计中使用了一种串联反馈结构的基带放大器以达到同时实现无源混频器输出缓冲,直流消除以及信号放大的功能. 实际测量显示,该接收机的输入1dB压缩点为-4dBm,当中频信号解调信噪比要求为10dB时,可达到的灵敏度为-70dBm. 该接收机与整个收发机集成在同一块芯片中,使用1.8V电源电压,工作时静态电流为90mA.     

一种用于900MHz射频识别(RFID)读写器芯片的1.8VCMOS直接变频接收机

设计了针对解决900MHz RFID读写器收发机芯片中本地载波干扰问题而优化的直接变频接收机,并在0.18μm 1P6M混合信号CMOS工艺上实现验证.设计中使用了一种串联反馈结构的基带放大器以达到同时实现无源混频器输出缓冲,直流消除以及信号放大的功能.实际测量显示,该接收机的输入1dB压缩点为-4dBm,当中频信号解调信噪比要求为10dB时,可达到的灵敏度为-70dBm.该接收机与整个收发机集成在同一块芯片中,使用1.8V电源电压,工作时静态电流为90mA.     

一种用于超高频RFID阅读器的正交下变频混频器的分析与设计

分析了共用跨导级的正交下变频混频器的性能,包括电压转换增益、线性度、噪声系数和镜象抑制比,分析表明其在电流开关模式下比传统的Gilbert混频器对具有更好的性能.设计并优化了一个基于共用跨导级结构的用于超高频RFID阅读器的正交下变频混频器.在915MHz频段上,该混频器测得12.5dB的转换增益,10dBm的IIP3 ,58dBm的IIP2和17.6dB的SSB噪声系数.芯片采用0.18μm 1P6M RF CMOS工艺实现,在1.8V的电源电压下仅消耗3mA电流.     

A dual-mode secure UHF RFID tag with a crypto engine in 0.13-μm CMOS

An ultra-high-frequency (UHF) radio frequency identification (RFID) secure tag chip with a non-crypto mode and a crypto mode is presented. During the supply chain management, the tag works in the non-crypto mode in which the on-chip crypto engine is not enabled and the tag chip has a sensitivity of -12.8 dBm for long range communication. At the point of sales (POS), the tag will be switched to the crypto mode in order to protect the privacy of customers. In the crypto mode, an advanced encryption standard (AES) crypto engine is enabled and the sensitivity of the tag chip is switched to +2 dBm for short range communication, which is a method of physical protection. The tag chip is implemented and verified in a standard 0.13-μm CMOS process.     

双频无源超高频实时定位系统研究

提出一种基于双频比相的无源超高频射频识别（UHF-RFID）实时定位系统（RTLS）。与传统射频识别定位系统相比,该方法带宽小,精度高。分析了双频比相测距原理在无源RFID系统中的适用性,通过理论计算得到非理想因素对测距精度的影响,并在Simulink平台上进行建模。仿真结果表明,I-Q相对失配度小于0.08,基带信噪比为21.5 dB时,系统定位精度可小于0.5 m。     

应用于接收机AGC环路中的SAR ADC

提出了一种应用于射频接收机自动增益控制(AGC)环路中的10位1 MS/s逐次逼近型模数转换器(SARADC).动态高精度比较器和自举开关技术应用在设计中,在保证转换速度和精度的同时,降低了电路功耗.芯片采用SMIC 0.13μm IP8M RF CMOS工艺实现.测试结果表明,在1.2 V电源电压下,采样率为1 MS...