一种高精度时钟同步电路

本文提出了一种基于交错延迟单元和动态补偿电路的高精度时钟同步电路结构,HPSC,并 可用在对时钟要求较高的大规模分布网络中。此电路采用了基于SMD的粗调结构和动态补偿 电路的细调结构,可在两个时钟周期内完成粗调并在接下来三个时钟周期内完成细调,其误 差小于3.8 ps。本电路使用SMIC 0.13 μm 1P6M 工艺设计并实现,供电电压1.2 V。其输入 频率为200MHz-800MHz,占空比为20%-80%,有效面积 245μm×134μm,功耗为1.64 mW@500MHz     

基于GA的步态特征与SVM参数协同优化研究

为了辅助医生对帕金森病患者进行更好的诊断,采用遗传算法对患者步态特征和支持向量机参数进行协同优化。在特征选择部分将步态特征和支持向量机参数使用二进制编码的方式生成染色体,同时输入到遗传算法中。考虑到遗传算法的搜索性能和运行时间,针对算法中的种群大小和进化代数这两个参数进行了寻优,找出合适的种群大小和进化代数。实验结果显示平均准确率为85.11%,相对于其他特征选择算法,准确率最高高出14%。表明使用该方法后对帕金森病患者的步态特征进行了有效去除,有利于患者的诊断。     

A fast transient response low dropout regulator with current control methodology

A transient performance optimized CCL-LDO regulator is proposed.In the CCL-LDO,the control method of the charge pump phase-locked loop is adopted.A current control loop has the feedback signal and reference current to be compared,and then a loop filter generates the gate voltage of the power MOSFET by integrating the error current.The CCL-LDO has the optimized damping coefficient and natural resonant frequency, while its output voltage can be sub-l-V and is not restricted by the reference voltage.With a 1μF decoupling capacitor,the experimental results based on a 0.13μm CMOS process show that the output voltage is 1.0 V;when the workload changes from 100μA to 100 mA transiently,the stable dropout is 4.25 mV,the settling time is 8.2μs and the undershoot is 5.11 mV;when the workload changes from 100 mA to 100μA transiently,the stable dropout is 4.25 mV,the settling time is 23.3μs and the overshoot is 6.21 mV.The PSRR value is more than -95 dB.Most of the attributes of the CCL-LDO are improved rapidly with a FOM value of 0.0097.     

基于注意力机制的TDNN-LSTM模型及应用

在大数据规模下,基于深度学习的语音识别技术已经相当成熟,但在小样本资源下,由于特征信息的关联性有限,模型的上下文信息建模能力不足从而导致识别率不高。针对此问题,提出了一种嵌入注意力机制层（Attention Mechanism）的时延神经网络（Time Delay Neural Network,TDNN）结合长短时记忆递归（Long Short Term Memory,LSTM）神经网络的时序预测声学模型,即TLSTM-Attention,有效地融合了具有重要信息的粗细粒度特征以提高上下文信息建模能力。通过速度扰动技术扩增数据,结合说话人声道信息特征以及无词格最大互信息训练准则,选取不同输入特征、模型结构及节点个数进行对比实验。实验结果表明,该模型相比于基线模型,词错误率降低了3.37个百分点。     

基于电流环路控制方法的快速响应LDO

LDO电路的瞬态响应能力是评价LDO性能的一个重要指标。本文借鉴电荷泵式锁相环的环路控制方法,提出了一种基于电流控制环路的LDO结构,将典型LDO电路中的电压比较改为电流比较,利用跨导放大器和环路滤波器产生功率管的控制栅压,使得环路具有优化的阻尼因子ζ和固有频率ωn,有效提高了LDO环路的瞬态响应能力,并且输出电压可以低至1V以下,且不受基准电压的限制。基于0.13μm CMOS工艺的实现结果表明,在使用1μF去耦电容,LDO输出1.0V的情况下,负载100μA→100mA瞬态变化时,输出超调5.11mV,稳定输出的压降4.25mV,稳定时间8.2μs,而负载100mA→100μA时,输出超调6.21mV,稳定输出的压降4.25mV,稳定时间23.3μs。结果表明,该电路各项性能指标均有明显的提高,FOM指数达到0.0097。     

A novel dual-feed low-dropout regulator

A novel dual-feed (DF) low-dropout (LDO) is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 μF decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.