一种增益与频率成正比的双频段正交压控振荡器

This paper presents a novel dual-band quadrature voltage controlled oscillator(VCO) with the gain proportional to the oscillation frequency.Frequency synthesizers with this VCO can reduce the bandwidth fluctuation over all the frequency ranges without compensation or calibration.Besides the original switched capacitor array, an extra switched varactor array is adopted for the implementation of the proposed VCO.The tuning technique of changing the values of the capacitor and varactor at the same ratio is also derived.For verification purposes, a 2.5 G/3.5 G dual-band quadrature VCO is fabricated in a 0.13μm CMOS process for WiMAX applications. Measurement results show that the VCO gain is closely proportional to the oscillation frequency with±16%variation over the entire frequency range.The phase noise is -138.15 dBc/Hz at 10 MHz from the 2.5 GHz carrier and -137.44 dBc/Hz at 10 MHz from the 3.5 GHz carrier.     

偶数级差分环形振荡器的稳定平衡态分析

与具有奇数增益级的差分环形振荡器不同,偶数级振荡器除了具有能够起振的非稳定平衡态,还有可能在起振前处于一种稳定平衡状态从而使电路锁定不能起振。该文主要分析了这种稳定平衡状态存在的原理,同时为了避免振荡器设计中的这种风险,提出了一种振荡器起振电路,使得电路在起振前处于接近非稳定平衡态的状态,从而能够快速起振。在0.13 m 1P8M 标准CMOS工艺下流片实现的4级差分环形压控振荡器(VCO)及其改进版本很好地验证了该文提出的理论和解决方法。经测试发现,第1款不带起振电路的4级VCO芯片锁定于稳定平衡态,不能起振;两种改进版本3级VCO和带起振电路的4级VCO都能够正常输出振荡信号。     

一种高精度的FPGA电路面积时序预测方法

在FPGA上设计应用电路时，逻辑综合过程和物理综合过程需要反复进行多次，来满足面积时序约束。为了加速整个FPGA CAD流程，本文提出了一种在物理综合之前，使用前馈神经网络预测面积时序的方法。和FPGA布局布线工具VTR7.0的实验结果相比，该神经网络预测面积平均相对误差（MRE）达到4.9%，预测时序平均相对误差（MRE）达到6.4%，和现有文献相比，具有预测时间早，预测精度高的特点。该预测模型将帮助用户缩短设计周期，在逻辑综合阶段更加全面探索设计空间，提高设计质量。     

A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA

A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.     

一种用于便携式射频识别阅读器的CMOS功率放大器

针对一种特定的射频识别技术的通讯协议(ISO1800-6B),提出了一种应用于射频识别读写器中的发射机前端结构,以实现发射信号的OOK调制.采用0.18μm CMOS工艺实现的这种高效率、高度集成的无线发射机前端由射频信号调制器、E类功率放大器以及相应的逻辑控制单元组成,其中的功率放大器的小信号增益约为23dB,其1dB压缩点输出功率为17.6dBm,最大输出功率为19.0dBm,而最大功率增加效率为35.4%.整个发射机的输出信号满足相应协议的特定要求,可以实现不同调制深度(18%和100%)的射频信号输出.     

一种用于便携式射频识别阅读器的CMOS功率放大器

针对一种特定的射频识别技术的通讯协议(ISO1800-6B),提出了一种应用于射频识别读写器中的发射机前端结构,以实现发射信号的OOK调制.采用0.18μm CMOS工艺实现的这种高效率、高度集成的无线发射机前端由射频信号调制器、E类功率放大器以及相应的逻辑控制单元组成,其中的功率放大器的小信号增益约为23dB,其1dB压缩点输出功率为17.6dBm,最大输出功率为19.0dBm,而最大功率增加效率为35.4%.整个发射机的输出信号满足相应协议的特定要求,可以实现不同调制深度(18%和100%)的射频信号输出.     

一种用于无线脑电信号检测系统的发射机电路

设计了一款应用于无线脑电信号(EEG)检测系统的射频发射机芯片。该发射机采用标准的0.18 μm CMOS工艺设计,主要包含锁相环(PLL)和功率放大器(PA)模块。锁相环电路中采用新型16/17预分频器结构以提高分频器的工作频率,同时压控振荡器采用数字调谐与模拟调谐相结合的方式拓宽了频率输出范围。测试结果显示,锁相环输出频率范围为2 225~2 580 MHz,锁定时间约为49 μs,发射机采用高效率E类功率放大器,最大输出功率达-3.14 dBm。发射数据采用二进制启闭键控(OOK)调制方式,最大传输速率可达5 Mbps。     

一种单电源高集成度蔡氏振荡器

二端非线性电阻的实现是研究蔡氏电路中混沌现象的一个重要环节,传统的非线性电阻大多采用正负电源供电的运放和电阻、电容等分立器件来搭建。在分析非线性电阻工作原理的基础上,提出采用单电源供电的集成电路制造工艺实现负阻器件的思想。设计的非线性负阻器件主要由轨到轨运算放大器、基准电压/电流产生等模块组成,并在0.18 μm标准CMOS工艺下设计实现。仿真结果表明,在1.8 V单电源工作模式下,蔡氏电路两个关键节点的李萨如波形表现为双螺旋吸引子,证明该振荡器电路有效,整个电路的功耗约为2.45 mA。     

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm². It achieves a sensitivity of -80 dBm for 10^-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.     

一种用于RFID读写器的高集成CMOS功率放大器的设计与分析

To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.