Monitoring of tool wear using measured machining forces and neuro-fuzzy modelling approaches during machining of GFRP composites

The challenges of machining, particularly milling, glass fibre-reinforced polymer (GFRP) composites are their abrasiveness (which lead to excessive tool wear) and susceptible to workpiece damage when improper machining parameters are used. It is imperative that the condition of cutting tool being monitored during the machining process of GFRP composites so as to re-compensating the effect of tool wear on the machined components. Until recently, empirical data on tool wear monitoring of this material during end milling process is still limited in existing literature. Thus, this paper presents the development and evaluation of tool condition monitoring technique using measured machining force data and Adaptive Network-Based Fuzzy Inference Systems during end milling of the GFRP composites. The proposed modelling approaches employ two different data partitioning techniques in improving the predictability of machinability response. Results show that superior predictability of tool wear was observed when using feed force data for both data partitioning techniques. In particular, the ANFIS models were able to match the nonlinear relationship of tool wear and feed force highly effective compared to that of the simple power law of regression trend. This was confirmed through two statistical indices, namely r² and root mean square error (RMSE), performed on training as well as checking datasets.     

Memory-based adaptive partitioning (MAP) of search space for the enhancement of convergence in Pareto-based multi-objective evolutionary algorithms

A new algorithm, dubbed memory-based adaptive partitioning (MAP) of search space, which is intended to provide a better accuracy/speed ratio in the convergence of multi-objective evolutionary algorithms (MOEAs) is presented in this work. This algorithm works by performing an adaptive-probabilistic refinement of the search space, with no aggregation in objective space. This work investigated the integration of MAP within the state-of-the-art fast and elitist non-dominated sorting genetic algorithm (NSGAII). Considerable improvements in convergence were achieved, in terms of both speed and accuracy. Results are provided for several commonly used constrained and unconstrained benchmark problems, and comparisons are made with standalone NSGAII and hybrid NSGAII-efficient local search (eLS).     

多选择软硬件划分问题的计算模型与动态规划算法

软硬件划分是软硬件协同设计的关键环节,划分的结果直接影响目标系统的设计质量。因此,对于一个给定的应用程序,为了使得目标系统快速执行且成本低廉,合理的划分策略十分重要。由于单个任务具有多种不同的硬件实现方式,与传统的单一硬件实现方式的软硬件划分问题相比,多选择的软硬件划分更能客观地反映现实应用。这导致问题的求解更具挑战性,它们已被证明是NP完全问题。基于多核处理器片上系统并针对任务图为二叉树的应用,建立了多选择软硬件划分问题的计算模型,并提出了解决该问题的动态规划算法。实验结果表明,当问题规模适中时,所提动态规划算法能够有效地获得精确解,并展示了算法的计算能力与硬件面积限制之间的关系。     

智能分区PID控制算法在电动缸伺服系统中的研究

针对电动缸伺服系统中的非线性环节,采用带线性补偿的分区二级前馈PID控制算法;首先建立电动缸伺服系统的仿真模型,并采用单组控制参数的二级前馈PID控制算法,通过仿真发现系统存在着抖动、精度较低的问题;然后提出了具有线性补偿的分区二级前馈PID控制算法,改进了相应的控制器结构并实现控制器的数字离散化;最后通过线性补偿的方法整定实际系统在各分区的控制参数,计算出相应的控制量;对比分析实际系统的稳态误差,发现智能分区PID控制器在电动缸伺服系统中能够取得更好的控制效果.     

基于多块结构网格大规模并行计算的负载均衡设计及实现

结构网格具有网格生成速度快、质量高、数据结构相对简单、较适用于流体表面应力集中的运算等优点。在大规模 CFD（Computational Fluid Dynamics）并行计算中,需要将网格区域划分为多块网格,而多块网格之间的数据通信会制约并行计算能力的提高,因此对结构网格的负载平衡优化是提高并行计算能力的重点。本文提出了一个采用多层次 k-way 多约束条件图剖分算法来改进负载平衡的方案,并对 M6 翼型和 CRM 模型的多种规模进行了实际计算,结果证明多层次 k-way图剖分算法能够有效地优化负载平衡,在此基础上得到了最优节点间的计算负载平衡和通信负载平衡,最终达到了理想的并行效率。     

支持过程级动态软硬件划分的RSoC设计与实现

目前,可重构计算平台所支持的动态软硬件划分粒度多处于线程级或指令级,但线程级划分开销太大,而指令级划分又过于复杂,因此很难被用于实际应用之中。本文设计并实现了一种支持过程级动态软硬件划分的可重构片上系统(RSoC),提出了一种过程级硬件透明编程模型,给出了过程级的硬件封装方案;在分析软硬件过程根本区别的基础上,针对硬件过程开发了专门的管理模块,并利用部分动态重构等技术,实现了硬件过程的动态配置。实验表明该系统能够较好的支持过程级的动态软硬件划分,实现了节省资源、简化设计,提高性能等目的。     

Efficient embedded wavelet codec based on list structure

A new efficient image codec called embedded wavelet coding based on list structure (EWCBL) is proposed in this paper. By combining the techniques of morphological representation and quadtree partitioning, EWCBL effectively exploits both within-subband clustering and cross-subband similarity of wavelet coefficients. Based on the list structure, a fine fractional bit-plane coding is employed to achieve excellent rate-distortion performance. The patterned morphological dilation is introduced to greatly reduce the redundant test operations. Experimental results show that the proposed EWCBL outperforms state-of-the-art embedded codecs for both lossy and lossless compression. Moreover, the good performance and features of embeddedness and scalability are achieved with relatively low complexity.     

One-dimensional partitioning for heterogeneous systems: Theory and practice

We study the problem of one-dimensional partitioning of nonuniform workload arrays, with optimal load balancing for heterogeneous systems. We look at two cases: chain-on-chain partitioning, where the order of the processors is specified, and chain partitioning, where processor permutation is allowed. We present polynomial time algorithms to solve the chain-on-chain partitioning problem optimally, while we prove that the chain partitioning problem is NP-complete. Our empirical studies show that our proposed exact algorithms produce substantially better results than heuristics, while solution times remain comparable.     

An architecture framework for an adaptive extensible processor

To improve the performance of embedded processors, an effective technique is collapsing critical computation subgraphs as application-specific instruction set extensions and executing them on custom functional units. The problem with this approach is the immense cost and the long times required to design a new processor for each application. As a solution to this issue, we propose an adaptive extensible processor in which custom instructions (CIs) are generated and added after chip-fabrication. To support this feature, custom functional units are replaced by a reconfigurable matrix of functional units (FUs). A systematic quantitative approach is used for determining the appropriate structure of the reconfigurable functional unit (RFU). We also introduce an integrated framework for generating mappable CIs on the RFU. Using this architecture, performance is improved by up to 1.33, with an average improvement of 1.16, compared to a 4-issue in-order RISC processor. By partitioning the configuration memory, detecting similar/subset CIs and merging small CIs, the size of the configuration memory is reduced by 40%.