Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I_D-V_G and I_D-V_D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.     

Power·delay product in COSMOS logic circuits

In this simulation work, we use COSMOS logic devices—a novel single gate CMOS architecture recently announced [1]—in multi-input logic gates, assessing its performance in terms of power·delay product. We consider three different multi-input logic circuits: a two-input NOR gate, a three-input NOR gate, and a three-input composite NOR/NAND (NORAND) gate. For this power·delay analysis, the transient TCAD simulations are employed in a mixed-mode approach where circuit and device simulations are coupled together, culminating in the delay response of the circuits as well as the static/dynamic current components. The analysis shows that all circuits, except the 3-input NOR gate, has acceptable characteristics at low-power applications and static leakage limits all COSMOS circuits at high-bias conditions.     

Confined acoustic phonons in ultrathin SOI layers

We try to reproduce experimental mobility curves in ultrathin silicon-on-insulator inversion layers using a Monte Carlo simulator and a bulk model for the electron scattering with acoustic phonons. While it is possible to reproduce the experimental behavior for the thicker samples, the electron mobility is strongly overestimated when the thinnest samples are considered. The mobility curves for the thinnest samples can be reproduced using the same model if the deformation potential parameter increases as the silicon thickness decreases. This fact shows that acoustic phonons are also confined in ultrathin silicon on insulator layers. We then study confined phonons in single and three layer structures in order to give a physical motivation to the increase of acoustic phonon scattering rate for in ultrathin silicon layers.     

SOI基光学电流传感器的设计与仿真

将光纤与微电子机械系统(MEMS)技术相结合,设计了一种新颖的检测50Hz高压交流电的光学电流传感器(OCS)。用ANSYS软件分析了器件的模态、动态响应与热膨胀特性,并通过Matlab软件模拟了器件的工作性能。模拟计算表明:ANSYS与理论公式得到的结果基本一致;传感器的量程为100~3600A,对于大电流下的灵敏度可达到0.02dB/A,温度变化±50K时传感器相应的测试误差为0.2%。     

Evaluation of graded-channel SOI MOSFET operation at high temperatures

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the g_m/I_DS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis.     

双面阶梯埋氧型SOI结构的耐压分析段宝兴

在单面阶梯埋氧型SOI结构的基础上,提出了一种双面阶梯埋氧SOI新结构.双面阶梯的电荷积累作用使其纵向电场突破了传统上受界面电荷为零限制的3倍关系,埋氧层的电场可以高达200V/μm;而且双面阶梯对表面电场的调制作用使其表面电场达到近乎理想的均匀分布.借助二维MEDICI数值分析软件,验证了此结构具有同时优化横向SOI基高压器件横、纵向电场,提高击穿电压的优点.     

Fabrication of thick BOX SOI by Smart-cut technology

A SOI material with thick BOX (2.2 μm) was successfully fabricated using the Smart-cut technology. The thick BOX SOI microstructures were investigated by high resolution cross-sectional transmission electron mi-croscopy (XTEM), while the electrical properties were studied by the spreading resistance profile (SRP). Experimen-tal results demonstrate that both structural and electrical properties of the SOI structure are very good.     

Reduction of self-heating effect in SOI MOSFET by forming a new buried layer structure

An inherent self-heating effect of the silicon-on-insulator (SOI) devices limits their application at high current Ievels. In this paper a novel solution to reduce the self-heating effect is proposed, based on N+ and O+ co-implantation into silicon wafer to form a new buried layer structure. This new structure was simulated using Medici program, and the temperature distnbution and output characteristics were compared with those of the conven-tional SOI counterparts. As expected, a reduction of self-heating effect in the novel SOI device was observed.     

在SOI材料上制备高质量的氧化铪薄膜

用电子束蒸发氧化铪靶的方法．在SOI(绝缘体上硅)材料上制备了氧化铪薄膜，随后在氮气中进行快速退火(600℃．300s)。借助掠角X射线衍射(GAXRD)、X射线光电子能谱(XPS)、高分辨透射电镜(HRTEM)技术分析了样品的微观结构．研究了样品在退火前后发生的组成及结构变化．结果表明退火后氧化铪薄膜由退火前的非晶态转变为单斜结构的多晶态，薄膜中的O／Hf原子比较退火前更接近化学计量比2。借助扩展电阻探针(SRP)技术考察了退火前后薄膜的电学性能．证明在SOI材料上制备的多晶氧化铪薄膜同样具有较好的电介质绝缘性能。     

Investigation of SiGe-on-Insulator Novel Structure

SiGe-on-Insulator (SGOI) is an ideal substrate material for realizing strained-silicon structures that are very competing and popular in present silicon technology. In this paper, two methods are proposed to fabricate SGOI novel structure. One is modified Separation by Implantation of Oxygen (SIMOX) starting from pseuodomorphic SiGe thin film without graded SiGe buffer layer. Results show that two-step annealing can improve the cystallinity quality of SiGe and block the Ge diffusion in high temperature annealing. SGOI structure with good quality has been obtained through two-step annealing. The second method is proposed to achieve SGOI with high content of Ge. High quality strained relax SiGe is grown on a compliant silicon-on-insulator (SOI) substrate by UHCVD firstly. During high temperature oxidation,Ge atoms diffuse into the top Si layer of SOI. We successfully obtain SGOI with the Ge content of 38%, which is available for the growth of strained Si.