Winner-Takes-All Associative Memory: A Hamming Distance Vector Quantizer

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.     

我国第一辆模拟分量电视转播车

本文简述了几种分量电视方式,着重介绍我国第一辆模拟分量电视转播车的系统设计、技术性能和特色以及经第十一届亚运会的实际运用考验,充分显示出该车系统的优越性,并证明了它与现行彩色电视制式具有良好的兼容牲。     

一种单刀双掷高速模拟开关的研制

介绍了一种单刀双掷高速模拟开关;描述了电路工作原理、线路设计、版图设计及可靠性设计。该高速模拟开关具有速度快、功耗低、隔离度高、关断漏电流小等特点。其内部电路设计有控制输入级、电平转换级、高速模拟开关管及静电保护电路。该电路可广泛应用于雷达接收机和发射机、通信系统和数据采集系统,以及通用模拟开关等领域。     

一种通用可编程数字频率合成器的设计

讨论了锁相式频率合成器的基本原理，设计了一种通用可编程锁相式频率合成器，介绍了其编程置型格式，提出了一种可提高程控分频器工作频率的电路设计方法，并给出了其模拟波形。该电路的最高合成频率为１００ＭＨｚ最小频率间隔为１００Ｈｚ，在工程上具有广泛的应用前景。     

反倾岩石边坡变形破坏试验及有限元分析

根据相似理论建立地质力学模型,研究反倾层状边坡岩体的变形破坏机制。介绍了模型试验的设计和过程,研究了原型边坡的变形破坏机制和岩层倾角对边坡稳定性的影响。同时进行了Ansys模拟计算。通过比较这两种研究方法的结果,发现反倾层状边坡岩体的变形机制为倾倒变形,破坏模式为弯折破坏;破坏首先在坡顶产生,边坡变形加速的过程是在开挖结束一段时间后才出现;岩层倾角的变化对反倾边坡的变形影响不敏感,但对边坡变形加速持续时间的长短有较大的影响,岩层倾角越小,变形加速所持续的时间越长。     

基于Proteus的电子电路设计探究

电子电路设计的一个重要环节,就包括电路功能实验调试,在具体设计中为了达到简化电路设计进程及缩短电路设计周期的目的,文章在设计分析典型函数信号发生器,四路彩灯（数字电视）和数显直流稳压电源时,使用了Proteus软件。进行分析设计之后得出,将Proteus运用在电子工程设计领域中的电子电路设计,能够达到省时省力省财目标的同时,还能够达到降低设计成本和提高设计效率的最终目标。     

Digital modular control of high frequency DC–DC converters

This paper presents a solution for controlling integrated DC–DC converters with high switching frequency (>20 MHz). The increase of the switching frequency is a trend biased by output filter volume restrictions and integration demand. The control of DC–DC converters operating at high frequency presents an opportunity to speed up the converter response time but also a challenge specially for the control solution, quiescent current and to limit the sensitivity to process and operating conditions for the mixed signal circuits involved. The solution presented in this work relies on separating the duty-cycle into three parts: a load-free value that depends only on the input and output voltages, a transient fast correction contribution, and an accurate compensation for the IR drop that depends on the load current. The load-free portion of the duty-cycle has a compensation of PVT variations and the fast transient part of the duty-cycle uses a non-linear sliding mode control solution. All the analog blocks required for the implementation of the proposed solution are detailed.     

Hybrid DPWM implementation using coarse and fine programmable ADLL

In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybrid DPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity with practical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay element is used to adjust the delay time of delay line and lock it to required time. The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based on shunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at a switching frequency of 352.8 kHz and clock generator frequency of 90.3 MHz allows us to attain SNR of 120 dB and THD of the output signal less than 0.1% within the audio baseband and modulation index M=0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for real CMOS process are presented.     

Mixed-grained CMOS field programmable analog array for smart sensory applications

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays （FPAAs）, which are the analogue counterparts of Field Programmable Gate Arrays （FPGAs）. In this paper, we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory micro- system. The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks （CABs） which house a variety of processing elements especially the proposed fine-grained Core Con- figurable Amplifiers （CCAs）. The high flexible CABs allow the FPAA operating in both continu- ous-time and discrete-time approaches suitable to support variety of sensors. To reduce the nonideal parasitic effects and save area, the fat-tree interconnection network is adopted in this FPAA. The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter. The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth. The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency. And the simulation results also show that the FPAA has good tolerance with wide PVT variations.