基于FPGA的GF(2~m)域求逆算法的设计研究

有限域GF(2m)上的椭圆曲线密码体制以其密钥短、安全强度高的优点获得了广泛的重视和应用,该密码体制域运算中最费时的运算是有限域上的求逆运算。论文提出一种基于多项式基乘法和平方的FPGA快速求逆设计方法,并给出了面积与速度的比较分析。     

有限域GF(2m)模逆算法的改进与实现

在椭圆曲线密码体制中,有限域GF(2m)中模逆运算是最重要的运算之一。在分析一种通用有限域GF(2m)模逆算法的基础上,提出改进算法。改进算法减少了原算法快速实现时的缺点,能够有效地提高算法效率。基于FPGA分别实现了GF(283)和GF(2233)中模逆算法模块,并与2种已有实现结果进行了对比。结果表明,选取有限域GF(283)和GF(2233)时,改进算法效率提高率分别约为72.9%和59.5%。     

基于GF(2m)域上Ⅱ型最优正规基的模乘算法及实现

论文提出了一种利用Ⅱ型正规基进行乘法运算的新方案。通过一种有效的线性变换,将GF(2^m)上的正规基转换成在GF(2^m)上的m项多项式。这种多项式可以使用任何多项式乘法算法进行相乘,然后再利用上述变换的逆过程将乘积转换回正规基。此方案所需的XOR和AND运算为M(m)+2mlog₂(m/2),其中M(m)取决于选用的多项式乘法算法。相较于其他的正规基乘法具有更小的资源占用量。通过FPGA综合实践表明,该方案能够显著减少LUTs数量。     

GF(2~m)域乘法器的快速设计及FPGA实现

有限域GF(2m)上的椭圆曲线密码体制以其密钥短、安全强度高的优点获得了广泛的重视和应用,该密码体制最主要的运算是有限域上的乘法运算。该文提出一种基于FPGA技术的多项式基乘法器的快速设计方法,并给出了面积与速度的比较分析。     

无移位操作的快速comb乘法算法

有限域GF(2n)上乘法运算是影响GF(2n)上椭圆曲线密码实现效率的关键运算之一.基于窗口技术的comb乘法算法,被认为是目前有限域GF(2n)上乘法运算最快的算法之一.但是,它仍然使用了移位操作,而移位操作恰好又是域GF(2n)乘法运算中很耗时的操作.提出并实现了一种新的基于窗口技术的快速comb乘法算法,该算法避免了移位操作,且不增加异或运算次数.理论分析和实验结果表明,新算法有很好的实现效率,适合于有限域GF(2n)上椭圆曲线密码算法的软件实现.     

正规基中模乘算法的FPGA实现方法研究

给出了GF(2m)上椭圆曲线密码系统中最佳正规基表示的模乘运算优化算法,提出了该算法的FPGA实现方案,并详细分析了实现该算法的有限状态机模型。结合Xilinx的FPGA器件,用VerilogHDL编写了实现该有限状态机的代码,在ISE和ModelSim开发工具中通过仿真、综合。试验表明,该文实现的模乘方案较其他实现方案具有较高的速度,并在EC-Elgamal密码体系中得到较好的应用。     

有限域GF(2~m)上ECDSA算法的优化

椭圆曲线数字签名算法(ECDSA)是数字签名算法(DSA)在椭圆曲线密码体制中的实现,其安全性依赖于椭圆曲线离散对数问题(ECDLP)的难解性。该文介绍了ECDSA在有限域GF(2m)上的实现,利用射影坐标思想,改进椭圆曲线上求两点和运算公式,对点乘算法进行优化,有效地提高了数字签名和签名验证的速度。     

一种通用GF(2~m)模乘加速器的快速实现

在椭圆曲线密码体制(ECC)中,有限域GF(2m)上模乘运算是最基本的运算,加速模乘运算是提高ECC算法性能的关键。针对不同不可约多项式广泛应用的现状,提出了一种通用GF(2m)模乘加速器设计方案。该加速器通过指令调度的方式,能快捷地完成有限域上模乘运算。实现结果表明,该设计完全适用于智能卡等应用要求。     

GF(2~m)上椭圆曲线密码体制的硬件实现

特征为2的有限域GF(2m)较适合椭圆曲线密码算法的硬件实现。该文通过对GF(2m)上模运算的分析,将所有的模运算转化成模乘和模加,并对LSD乘法器的进行了改进,所设计的运算单元能进行GF(2m)上所有的模运算,利用该运算单元所实现的椭圆曲线密码算法具有面积小,速度快的优点,适合用于处理能力和存储空间受限的设备中。     

GF(2~n)域上基于ONB的ECC芯片设计与实现

分析了GF(2~n)域上的椭圆曲线的运算法则,提出了一种串-并行结构的基于优化正规基(ONB)的高速有限域运算单元,比较了域划分D对芯片实现速度和硬件资源占用的影响,完成了域GF(2191)上基于ONB的ECC芯片快速实现。FPGA验证表明,GF(2191)域上一次点加运算需要183个时钟,一次点倍运算需要175个时钟,完成一次求乘法逆运算的总时钟数为133。在50MHz时钟下,完整的点乘运算速度平均为981次/s。     

Partition Algorithm For Parallel Processing Of Array Multiplication In Gf(2m) Fields

The multiplication operations in GF(2m) fields are widely used in cryptosystems. However, the multiplication operations for public-key cryptosystems require very large operands with 512 bits or more, and then existing multipliers are not available for such multiplications. In this paper, we will present a partition algorithm to divide large operands into small operands such as 32 bits or 64 bits, and then existing multipliers can be employed. We also present a parallel version of the partition algorithm by employing an important natural property of the multiplication operations in GF(2m) fields.     

VLSI architectures for computing multiplications and inverses in GF(2m)

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.     

Applying systolic multiplication–inversion architectures based on modified extended Euclidean algorithm for GF(2) in elliptic curve cryptography

Elliptic curve cryptography is a very promising cryptographic method offering the same security level as traditional public key cryptosystems (RSA, El Gamal) but with considerably smaller key lengths. However, the computational complexity and hardware resources of an elliptic curve cryptosystem are very high and depend on the efficient design of EC point operations and especially point multiplication. Those operations, using the elliptic curve group law, can be analyzed in operations of the underlined GF(2^k) Field. Three basic GF(2^k) Field operations exist, addition–subtraction, multiplication and inversion–division. In this paper, we propose an optimized inversion algorithm that can be applied very well in hardware avoiding well known inversion problems. Additionally, we propose a modified version of this algorithm that apart from inversion can perform multiplication using the architectural structure of inversion. We design two architectures that use those algorithms, a two-dimensional multiplication/inversion systolic architecture and an one-dimensional multiplication/inversion systolic architecture. Based on either one of those proposed architectures a GF(2^k) arithmetic unit is also designed and used in a EC arithmetic unit that can perform all EC point operations required for EC cryptography. The EC arithmetic unit’s design methodology is proposed and analyzed and the effects of utilizing the one or two-dimensional multiplication/inversion systolic architecture are considered. The performance of the system in all its design steps is analyzed and comparisons are made with other known designs. We manage to design a GF(2^k) arithmetic unit that has the space and time complexity of an inverter but can perform all GF(2^k) operations and we show that this architecture can apply very well to an EC arithmetic unit required in elliptic curve cryptography.     

一种基于有限域的快速乘法器的设计与实现

基于有限域上椭圆曲线公开密匙协议的离散对数计算算法正日益成为热点，而有限域上的计算尤其是乘法计算极大地影响其加／解密速度。为了提高椭圆曲线密码系统的计算速度，需要从很多方面考虑，但其中关键的一点在于如何提高乘法器的速度，且保持其规模在能够接受的范围。在对椭圆曲线的分析基础上提出了一种有限复合域GF((2^m1)^m2)上的快速乘法器。该乘法器采用并行计算和串行计算相结合的原则，在增加少量硬件规模将一次有限域乘法的计算速度由原来的m=m2m1个时钟周期降低到m2个时钟周期，从而极大地提高了乘法器的计算速度。通过FPGA的验证测试证明该方法在速度上完全适合椭圆曲线密码系统。     

Design of Montgomery Multiplication Architecture Based on Programmable Cellular Automata

This study presents a Montgomery multiplication architecture that uses an irreducible all one polynomial (AOP) in GF(2 ^m ) based on a programmable cellular automata (PCA). The proposed architecture has the advantage of high regularity and a reduced latency based on combining the characteristics of the irreducible AOP and PCA. The proposed architecture can be used to implement modular exponentiation, division, and inversion architectures.     

Low-Complexity Bit-Parallel Multiplier over GF(2$^m$) Using Dual Basis Representation

Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF（2^m） using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is presented, The architecture is optimized in order to minimize the silicon covered area （transistor count）. The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF（2^m）.     

一种基于Grobner基的代数攻击方法

代数攻击能够有效分析出分组密码中的密钥值,Grobner基能够快速求解多变量高次方程组。该文提出一种基于Grobner基的代数攻击方法,用超定代数方程组描述Rijndael加密算法,采用项序转换算法FGML将次数反字典序转化为字典序,使算法能够在已知少量明密文对的情况下对密钥进行求解,通过设计合理的项序和方程组解的判定降低算法复杂度。     

Selection of Secure Hyperelliptic Curves of g = 2 Based on a Subfield

In the implementation of hyperelliptic curve cryptosystems, a siginificant step is the selection of secure hyperelliptic curves on which the Jacobian is constructed. In this paper, we discuss the hyperelliptic curves of g=2 such as v2 uv=f and v2 v=f(u) defined on GF(2r). The curves defined on GF(4) and GF(8) are expanded to the curves defined on GF(4)k and GF(8)t respectively, where 38相似文献