并行视频服务器体系结构研究

分析了目前流行的并行视频服务器体系结构：分布式结构、集群式结构、并行通用计算机结构和并行专用视频服务器结构。综合其优点，针对视频应用的特点，提出了可扩展并行视频服务器体系结构，并研制了基于该结构的并行服务系统。     

面向嵌入式应用的数据并行语言设计

根据基于PIM(Processor-In-Memory)技术的数据并行计算机体系结构的特点和面向多媒体计算的应用需求,提出了面向嵌入式SIMD(Single Instruction Multiple Data)计算的数据并行语言PIMC。简单讨论了PIMC语言的形式化定义,并以数据并行图像处理的均值滤波算法为例对语言的使用作了说明。结合其他大量的数据并行编程实例,说明了该语言能够在基于PIM技术的SIMD并行计算机上正确描述基本多媒体处理算法的数据并行实现。     

面向神经计算的并行机体系结构设计

面向神经计算的并行计算机体系结构是神经网络研究中的一项重要工作。本文在对大量的神经计算进行需求分析的基础上，讨论了以高性能的微处理器作为计算单元，进行面向神经计算的并行计算机体系结构设计，并且介绍了它原型实现的结构、参数和性能     

基于并行PC结构的操作系统模型研究

1.引言并行PC是针对未来高端个人机、工作站设计的,面向实时多媒体应用的新型计算机体系结构。传统计算机采用总线结构,以主存为中心,采用集中式控制策略,其缺陷在于总线结构形成通信瓶颈,集中式控制造成控制瓶颈,成为限制计算机性能进一步提高的障碍。并行PC是针对传统计算机结构的缺陷,综合考虑     

环行阵列神经网络计算机系统

文中首先考察了神经网络计算和并行计算机的特点,提出了环行阵列体系结构,泽环行阵列体系结构和Ｓｙｓｔｏｌｉｃ结构进行了比较。提出了基于环行阵列体系结构的神经网络计算的并行算法,并对该算法的性能进行了分析。     

光学可重排全交叉—逆全交叉网络及其与Benes网络拓扑等价的…

互连网络是数字光计算机及并行电子计算机体系结构的重要研究课题。本文提出了可重排全交叉－逆全交叉网络的拓扑结构及其光学实现方案。并采用互连网络拓扑等价的图分析法得到了全交叉－逆全交叉网络与Ｂｅｎｅｓ网络具有拓扑等价性质的多套逻辑名结构。为开拓光学可重排人交叉－逆全交叉网络在光电混合巨型并行多处理计算机系统潜在应用提供了理论依据。     

数据并行计算机体系结构建模

分析并研究国内外典型的数据并行计算机体系结构建模,结合LS-MPP计算机的体系结构,提出一种基于二维阵列结构的SIMD计算机抽象模型。通过对逻辑部件的时序分析,实现关于该模型的解释型SIMD仿真器,在进行细粒度时钟精确级建模时兼顾仿真效率。仿真器测试结果表明,该抽象模型具有一定应用价值。     

用MDA方法实现CORBA体系结构

为了解决软件可重用问题，OMG发布了模型驱动体系结构（MDA）。MDA认为系统开发的最好方式是隔离系统设计与系统实现，独立建模业务行为和领域元素，关注系统应用本身而不是将中间件平台作为系统开发的中心。它将系统结构化成PIM和PSM模型，通过映射和转换机制将PIM转换成PSM并不断求精，最后生成代码。文中以“香港利苑集团餐饮管理系统”为背景，介绍利用MDA方法开发CORBA系统。     

支持无共享结构的并行DBMS软件结构

文中介绍并行数据库系统ＰＡＲＯ的体系结构设计，它能很好地支持无共享结构的并行计算机。并描述该系统的软件结构，说明如何在这一软件结构下开发事务间并行性、查询内的操作间和操作内并行性。     

用MDA方法实现CORBA体系结构

为了解决软件可重用问题,OMG发布了模型驱动体系结构(MDA)。MDA认为系统开发的最好方式是隔离系统设计与系统实现,独立建模业务行为和领域元素,关注系统应用本身而不是将中间件平台作为系统开发的中心。它将系统结构化成PIM和PSM模型,通过映射和转换机制将PIM转换成PSM并不断求精,最后生成代码。文中以“香港利苑集团餐饮管理系统”为背景,介绍利用MDA方法开发CORBA系统。     

十亿晶体管处理器体系结构研究

半导体工艺技术的飞速发展促使单芯片内集成有更多的晶体管资源。如何利用丰富的片上资源，已成为处理器体系结构研究的一个重点。本文综述了目前关于十亿晶体管处理器结构的研究现状，认为在缓解当前处理器面临的存储墙问题、功耗问题、线延迟问题以及充分利用片上资源等方面，PIM结构是一种有效的途径，而与向量结构相结合则更
能体现PIM结构的高带宽．低延迟优势。     

SAGE: an automatic analyzing system for a new high-performance SoC architecture––processor-in-memory

Continuous improvements in semiconductor fabrication density are supporting new classes of System-on-a-Chip (SoC) architectures that combine extensive processing logic/processor with high-density memory. Such architectures are generally called Processor-in-Memory (PIM) or Intelligent Memory (I-RAM) and can support high-performance computing by reducing the performance gap between the processor and the memory. The PIM architecture combines various processors in a single system. These processors are characterized by their computation and memory-access capabilities. Therefore, a novel strategy must be developed to identify their capabilities and dispatch the most appropriate jobs to them in order to exploit them fully. Accordingly, this study presents an automatic source-to-source parallelizing system, called statement-analysis-grouping-evaluation (SAGE), to exploit the advantages of PIM architectures. Unlike conventional iteration-based parallelizing systems, SAGE adopts statement-based analyzing approaches. This study addresses the configuration of a PIM architecture with one host processor (i.e., the main processor in state-of-the-art computer systems) and one memory processor (i.e., the computing logic integrated with the memory). The strategy of the SAGE system, in which the original program is decomposed into blocks and a feasible execution schedule is produced for the host and memory processors, is investigated as well. The experimental results for real benchmarks are also discussed.     

Performance based design of high-level language-directed computerarchitectures

This paper is concerned with the analytical modeling of computer architectures to aid in the design of high-level language-directed computer architectures. High-level language-directed computers are computers that execute programs in a high-level language directly. The design procedure of these computers are at best described as being ad hoc. In order to systematize the design procedure, we introduce analytical models of computers that predict the performance of parallel computations on concurrent computers. We model computers as queueing networks and parallel computations as precedence graphs. The models that we propose are simple and lead to computationally efficient procedures of predicting the performance of parallel computations on concurrent computers. We demonstrate the use of these models in the design of high-level language-directed computer architectures.     

The serial performance standards for the BBS test program

ESPRIT Project 5417 - BECAUSE - is concerned with the benchmarking of parallel computer architectures for computer intensive scientific and engineering applications. Fluid flow, semi-conductor modelling and electromagnetic field simulation software was profiled on a range of example applications and sizes. The profiling results were used to select the algorithms and functions that ought to be included in the Because Benchmark Set (BBS). This paper reviews the BBS results obtained on the ·control’ sequential architecture computer. The results show consistent performance with some interesting variations in achieved Mflops.     

基于软件模式的PIM到PSM的模型变换

模型驱动体系结构(MDA)是一种以模型为中心的新的软件开发模式。MDA的基本思想是将模型主要分为平台无关模型(PIM)和平台相关模型(PSM),然后通过变换规则实现PIM到PSM的变换。文中将软件模式的概念引入到PIM到PSM模型变换中,从而提高模型变换效率和降低模型变换出错率。同时,设计了基于软件模式的PIM到PSM的模型变换方法的框架。     

基于计算机技术的并行测试实现方法研究

并行测试已成为未来自动测试领域的发展趋势,而计算机技术的飞速发展为并行测试提供了许多思想和实现方法;在给出理想的并行测试结构框架后,文中着重从计算机技术应用的角度论述了并行测试的方法;多处理器和单处理器并行测试结构成为并行测试的两种主要体系,这其中又具体为分布式并行测试结构,协处理器结构,以及多进程、多线程结构等;这些结构体系各有特点,在搭建并行测试系统时应适情况选取,以便更大程度地提高测试速度、效率,节约测试资源.     

计算机体系结构的分类模型

根据计算机体系结构的发展,以指令流（instruction stream）计算、数据流（data stream）计算与构令流（configuration stream）计算的概念为基础,提出了一种新的计算机体系结构的分类模型.     

SCMP: A Single-Chip Message-Passing Parallel Computer

As technology improves and transistor feature sizes continue to shrink, the effects of on-chip interconnect wire latencies on processor clock speeds will become more important. In addition, as we reach the limits of instruction-level parallelism that can be extracted from application programs, there will be an increased emphasis on thread-level parallelism. To continue to improve performance, computer architects will need to focus on architectures that can efficiently support thread-level parallelism while minimizing the length of on-chip interconnect wires. The SCMP (Single-Chip Message-Passing) parallel computer system is one such architecture. The SCMP system includes up to 64 processors on a single chip, connected in a 2-D mesh with nearest neighbor connections. Memory is included on-chip with the processors and the architecture includes hardware support for communication and the execution of parallel threads. Since there are no global signals or shared resources between the processors, the length of the interconnect wires will be determined by the size of the individual processors, not the size of the entire chip. Avoiding long interconnect wires will allow the use of very high clock frequencies, which, when coupled with the use of multiple processors, will offer tremendous computational power.     

SNAP: parallel processing applied to AI

It is argued that a viable solution for building future intelligent systems is to design special-purpose parallel computer architectures. The applications are restricted to those using semantic networks for knowledge representation. Reasoning on these networks is achieved with a marker-passing model of processing. The Semantic Network Array Processor (SNAP), a marker-passing parallel computer dedicated for natural-language and other knowledge-processing applications, is considered. Solutions for several nontrivial natural-language problems using the marker-passing approach are discussed