CMOS单元电路版图的自动设计

本文描述了ＣＭＯＳ单元电路版图自动设计程序是自动电路版图设计系统的一个组成部分，它通过一列变换，将单元电器描述翻译成单元电路版图的几何描述。其特点是允许单元内多端口线网布和允许在单元四周指定端口，并对单元电路版图进行优化，因此，只要输入单元电路描述，便可自动产生单元电路的版图文件。     

Computer Aids for IC Design

Talib augments existing algorithmic techniques with domain-specific knowledge to automate NMOS IC cell layout. Its efficiency rating is within five percent of layouts generated manually.     

基于状态机的ROM接口电路模型

在芯片设计中会经常使用到ROM,而ROM又经常作为片外存储器被所设计的芯片进行读写操作,在这里就需要设计接口电路用来配合ROM和设计的芯片。ROM多为异步工作方式,如果设计的电路为同步电路,之间又存在着接口时序配合的问题。文中介绍一种基于状态机的ROM接口电路模型。该模型有两个特点:一是采用状态机实现同步时序电路与ROM异步时序电路的接口时序配合;二是实现与具有不同时间参数ROM接口电路的兼容。该模型的设计结果通过了FPGA验证,并在ASIC芯片中得到运用。     

集成电路中的天线效应

天线效应会在MOS集成电路制造中引起良率和可靠性的问题,当芯片尺寸在深亚微米以下的工艺中更容易产生.介绍了集成电路中天线效应产生的原理,以及在版图设计中为避免天线效应所常用的几种方法.     

CD-ROM/DVD马达驱动电路的设计与开发

本文介绍了一种CD-ROM/DVD马达驱动IC的设计和简洁地介绍了其职能。为例AM5954,本文给出了主要功能模块的电压基准的工作原理,热保护电路,当前的传输电路和级联与数学推导运算放大器。委员会还讨论了布局设计,尤其是困难和一个马达驱动集成电路布图设计的重点,提供相应的解决方案。     

The Magic VLSI Layout System

Magic is a new IC layout system that includes several facilities traditionally contained in separate batch-processing programs. Magic incorporates expertise about design rules, connectivity, and routing directly into the layout editor and uses this information to provide several unusual features. They include a continuous design-rule checker that operates in background and maintains an up-to-date picture of violations; a hierarchical circuit extractor that only re-extracts portions of the circuit that have changed; an operation called plowing that permits interactive stretching and compaction; and a suite of routing tools that can work under and around existing connections in the channels. A design style called logs and a data structure called corner stitching are used to achieve an efficient implementation of the system.     

分层构造方法在建筑平面布局中的应用

分层构造的自动造型方法针对方案设计过程由抽象到具体、由模糊到精确的特点，支持从概念到形状的方案设计全过程。分析了建筑平面布局设计过程中不同抽象层次和不同求解阶段的特点，应用分层构造的方法建立了一个以辅助方案设计为核心的建筑平面布局CAD实验系统。     

基于SS序列集成电路布线技术

集成电路(IC)是在半导体基片上形成的完整的电子线路。当前芯片里的电路与系统日趋复杂,超大规模集成电路(VLSI)设计技术水平也在逐渐提高。VLSI设计中一般采用分级设计的方法。布图设计过程是整个VLSI分级设计中非常关键的步骤之一。基于Single-Sequence的集成电路布图就是在SS编解码的应用下对芯片中各单元的摆放进行优化从而达到芯片面积利用率最大化。本文重点介绍了在SS序列生成版图后各单元间连线的设计以及如何根据水平/垂直约束图提取版图中各单元的坐标。并根据要连模块的位置关系对其连线经过的模块进行有条件加线宽的处理。     

An extraction-based verification methodology for MEMS

Micromachining techniques are being increasingly used to develop miniaturized sensor and actuator systems. These system designs tend to be captured as layout, requiring extraction of the equivalent microelectromechanical circuit as a necessary step for design verification. This paper presents an extraction methodology to (re-)construct a circuit schematic representation from the layout, enabling the designer to use microelectromechanical circuit simulators to verify the functional behavior of the layout. This methodology uses a canonical representation of the given layout on which feature-based and graph-based recognition algorithms are applied to generate the equivalent extracted schematic. Extraction can be performed to either the atomic level or the functional level representation of the reconstructed circuit. The choice of level in hierarchy is governed by the trade off between simulation time and simulation accuracy of the extracted circuit. The combination of the MEMS layout extraction and lumped-parameter circuit simulation provides MEMS designers with VLSI-like tools enabling faster design cycles, and improved design productivity     

基于SS序列集成电路布线技术

集成电路（IC）是在半导体基片上形成的完整的电子线路。当前芯片里的电路与系统日趋复杂,超大规模集成电路（VLSI）设计技术水平也在逐渐提高。VLSI设计中一般采用分级设计的方法。布图设计过程是整个VLSI分级设计中非常关键的步骤之一。基于Single-Sequence的集成电路布图就是在SS编解码的应用下对芯片中各单元的摆放进行优化从而达到芯片面积利用率最大化。本文重点介绍了在SS序列生成版图后各单元间连线的设计以及如何根据水平／垂直约束图提取版图中各单元的坐标。并根据要连模块的位置关系对其连线经过的模块进行有条件加线宽的处理。     

Layout aid for the design of VLSI circuits

VLSI (very large scale integration) circuits are the most complex chips yet developed, typically having over 50 000 transistors. Some examples are a 16 kbit static RAM chip or a 16 bit microprocessor chip. The complexity of these chips necessitates the invention of new techniques in order to reduce production costs and design time.The design cycle of an IC (integrated circuit) consists of a series of complex tasks often requiring more than a year to complete. As ICs grow in complexity, the cycle time increases and could potentially become too lengthy to be realistic. One of the most time consuming tasks in the design cycle is laying out a circuit. This paper describes a new layout aid that will significantly reduce the layout time.In this new layout aid, a designer is required to digitize an approximate layout, fully routed but loosely placed. From this approximate layout, two graphs are created, one representing the relative vertical position of each circuit element in the loose sketch, and the other representing their relative horizontal position. In the graphs, modes indicate the coordinate locations and branches indicate minimum spacing requirements due to design rules. An optimization technique, namely the longest path algorithm, is invoked to compact the circuit. In the original layout, design rule violations may be overlooked, which will prevent the longest path algorithm from converging. A method is devised to resolve this problem. Results of empirical testing of the new layout aid are reported.     

基于功能面的产品布局与人机工程协同设计的研究

在产品概念设计中,布局设计和人机工程设计是两个相互影响和制约的设计过程,。为了将这种布局设计和人机工程设计协同起来,将功能面作为概念设计发解的依据,并在此基础上提出了基于功能面的协同概念设计过程和方法,以及布局设施 人机工程协同设计模型和形式化描述方法,最后结合摩托车的概念设计实例给出了一个计算机支持的布局和人机工程协同设计系统的实现方案。     

基于晶体管级参数提取的后仿真

介绍了时钟电路芯片的功能,给出了Star-RCXT(RC参数提取工具)的晶体管级参数提取及后仿真流程,详细描述了一些基于晶体管级参数提取的版图后仿真设计经验,给出了设计的前、后仿真的输出对比结果.