FPGA动态部分可重构技术概述

可重构计算是一种新的计算结构,它将通用处理器和专用集成电路的优点结合起来,具有灵活、高效的特点。FPGA的动态部分可重构是指在系统运行中对FPGA的部分逻辑资源实现动态的功能变换,从而提高数字系统集成度、增强灵活性、提升容错能力,同时降低成本和功耗。本文主要介绍FPGA动态部分可重构的原理以及实现动态部分可重构的方法,并着重分析4种常用的实现方法;介绍FPGA动态部分可重构技术目前在国内外的最新发展和应用;对FPGA动态部分可重构的未来研究发展方向做简单介绍。      

UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems

The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing environment conditions. However, this new dimension of dynamic hardware reconfigurability has rendered existing CAD tools and platforms incapable of efficiently exploring the design space. As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS). Computation-intensive network security functions, implemented as reconfigurable hardware functions, can be configured on-demand into a DPRNSS at run-time. Thus, UCoP not only supports dynamic adaptation to different environment conditions, but also increases hardware resource utilization. UCoP supports design space exploration for reconfigurable systems in three folds. Firstly, it provides reusable models of typical reconfigurable systems that can be customized according to user applications. Secondly, UCoP provides a partially reconfigurable hardware task template, using which users can focus on their hardware designs without going through the full partial reconfiguration flow. Thirdly, UCoP provides direct interactions between UML system models and real reconfigurable hardware modules, thus allowing accurate time measurements. Compared to the existing lower-bound and synthesis-based estimation methods, the accurate time measurements using UCoP at a high abstraction level can more efficiently reduce the system development efforts.     

Real Time Image Rotation Using Dynamic Reconfiguration

Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and performance. It appears that, according to the nature of the application, the dynamic reconfiguration can be less or more advantageous. In order to be able to test the validity of our approach in terms of algorithm and architecture adequacy, we realized an AT40K40-based board “ARDOISE”.     

基于动态可重构技术的装备测试系统研究

当前国内自动测试系统存在实时性差、测试资源冗余、成本高等问题,针对以上问题,提出了基于FPGA部分动态重构技术的自动测试系统,该系统基于FPGA动态可重构技术并结合嵌入式操作系统实现测试资源的动态管理,并开发了用于测试过程的硬件自动测试任务编程模型,提出了一种用于重构任务加载的ICAP控制器;该系统实现测试过程的并发执行,从而增强自动测试系统测试的实时性,进而提高测试的准确性与覆盖性。在验证试验中,将动态重构测试系统应用于自动测试实例中,试验结果表明硬件重构测试任务加载正常,各测试资源功能执行正确     

Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems

Reconfigurable architectures are increasingly often applied in various industrial data processing applications, due to the possibility for performing parallel computations and achieving a simplified Systemon-Chip design flow. Furthermore, the exploitation of dynamic and partial hardware reconfiguration has been investigated in different research projects, often in systems based on Xilinx Virtex 2/4 FPGA families, by time-multiplexing hardware resources for multiple functions. This paper describes the exploitation of partial reconfiguration for dynamic power management in a low-power Spartan 3-based level measurement application. The reconfiguration process is thereby applied to optimize system implementation according to the applications requirements on power consumption and performance.     

基于FPGA的拟态服务器设计

随着计算机技术的不断发展,传统架构下的CPU处理能力已无法应对日益多样化的计算处理任务,新型异构计算体系也存在可提升的空间.分析了以“应用决定结构,结构决定效能”为理念,基于多维重构函数化结构与动态多变体运行机制的拟态计算（Mimicry Computing,MC）体系架构,利用FPGA硬件可编程、动态可重构和功耗低的特性,设计了一种基于FPGA的拟态计算服务器,并阐明了该服务器的核心电路设计与关键技术实现.     

可重构资源管理及硬件任务布局的算法研究

可重构系统具有微处理器的灵活性和接近于ASIC的计算速度,可重构硬件的动态部分重构能力能够实现计算和重构操作的重叠,使系统能够动态地改变运行任务,可重构资源管理和硬件任务布局方法是提高可重构系统性能的关键.提出了基于任务上边界计算最大空闲矩形的算法(TT-KAMER),能够有效地管理系统的空闲可重构资源;在此基础上使用FF和启发式BF算法进行硬件任务的布局.实验表明,算法能够有效地实现在线资源分配与任务布局,获得较高的资源利用率.     

动态重构硬件加速中的性能开销建模

近年来,随着可重构计算方法和可重构硬件特性的不断演进,基于FPGA动态部分重构技术构建运行时可重构加速器已经成为解决传统加速器设计中硬件资源限制问题的重要途径.然而,区别于传统静态重构加速器,FPGA的动态重构开销是影响硬件加速整体性能的重要因素,而目前尚缺少能够在可重构硬件设计的早期阶段进行动态重构开销精确估算的相关...     

Architecture and operating system support for two-dimensional runtime partial reconfiguration

Reconfigurable machines based on field programmable gate array (FPGA) chips adapt to applications’ needs through hardware reconfiguration. Partial reconfiguration allows the configuration of a portion of a chip while the rest of the chip is busy working on tasks. This paper considers a two-dimensional partially reconfigurable FPGA chip that allows the dynamic swap in and out of circuit modules. Such a chip supports the concurrent execution of multiple applications or an application that is otherwise too large to fit. A challenging issue for 2-D runtime partial reconfiguration is how to support the efficient connection, or routing, between circuit modules or between modules and I/O pins, when those modules may be placed on any area of a chip. Because commercial chips are not efficient in 2-D runtime routing, a new FPGA architecture is proposed based on an array of clusters of configurable logic blocks and a mesh of segmented buses. To evaluate the runtime performance of the architecture, an operating system is specified and implemented which takes care of the scheduling, placement, and routing of circuits on the architecture. Simulation is used to evaluate the efficiency of the OS kernel and to determine the optimal cluster size of the architecture.     

动态部分可重构方法在SDRAM控制器中的应用

动态部分可重构方法应用于FPGA系统设计中,充分利用了FPGA芯片提供的可重配置功能,减小了FPGA芯片的配置时间。通过对可重构方法的研究,提出了基于模块化动态可重构方法应用到SDRAM控制器设计中,给出了重构流程,并对实验结果进行了分析。该方法提高了FPGA芯片的利用率,有效地提高了可重配置计算系统的整体性能。     

Elastic superposition task mapping for NoC-based reconfigurable systems

With technology progress, more and more applications are integrated into a single chip. This requires a large number of processing elements (PEs) in a system, such that computation can be effectively enhanced through parallel processing. To support more efficient parallel processing, the Network-on-Chip (NoC) is being increasingly adopted as an interconnection architecture. Nevertheless, for NoC-based reconfigurable systems, the issue of mapping tasks to the PEs becomes more complex, due to the characteristic of hardware reconfiguration. This work proposes a novel Elastic Superposition Mapping (ESM) that introduces a useful PE reservation heuristic along with dynamic cross-application superposition. The ESM can provide a great elasticity for an NoC-based reconfigurable system to map more applications. Thus, the task load on PE will increase. Experiments show that, compared to the state-of-the-art mapping methods, 7% to 49% more applications can be executed, the average task load on PE can be increased by 5.5% to 56%, and the application waiting time can be reduced by 11% to 54%.     

Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system

There are many design challenges in the hardware-software co-design approach for performance improvement of data-intensive streaming applications with a general-purpose microprocessor and a hardware accelerator. These design challenges are mainly to prevent hardware area fragmentation to increase resource utilization, to reduce hardware reconfiguration cost and to partition and schedule the tasks between the microprocessor and the hardware accelerator efficiently for performance improvement and power savings of the applications.In this paper a modular and block based hardware configuration architecture named memory-aware run-time reconfigurable embedded system (MARTRES) is proposed for efficient resource management and performance improvement of streaming applications. Subsequently we design a task placement algorithm named hierarchical best fit ascending (HBFA) algorithm to prove that MARTRES configuration architecture is very efficient in increased resource utilization and flexible in task mapping and power savings. The time complexity of HBFA algorithm is reduced to O(n) compared to traditional Best Fit (BF) algorithm’s time complexity of O(n²), when the quality of the placement solution by HBFA is better than that of BF algorithm. Finally we design an efficient task partitioning and scheduling algorithm named balanced partitioned and placement-aware partitioning and scheduling algorithm (BPASA). In BPASA we exploit the temporal parallelism in streaming applications to reduce reconfiguration cost of the hardware, while keeping in mind the required throughput of the output data. We balance the exploitation of spatial parallelism and temporal parallelism in streaming applications by considering the reconfiguration cost vs. the data transfer cost. The scheduler refers to the HBFA placement algorithm to check whether contiguous area on FPGA is available before scheduling the task for HW or for SW.     

A theory for deadlock-free dynamic network reconfiguration. Part I

This paper develops theoretical support useful for determining deadlock properties of dynamic network reconfiguration techniques and also serves as a basis for the development of design methodologies useful for deriving deadlock-free reconfiguration techniques. It is applicable to interconnection networks typically used in multiprocessor servers, network-based computing clusters, and distributed storage systems, and also has potential application to system-on-chip networks. This theory builds on basic principles established by previous theories while pioneering new concepts fundamental to the case of dynamic network reconfiguration.     

Parameterization of efficient dynamic reconfigurable trees

We present an algorithm for dynamic reconfiguration from a set of processor nodes connected using a multistage interconnection network into a set of m-ary trees of height h. The algorithm allows parameterization based on the branching factor m, the height of the tree h and bias B and produces a set of isomorphic trees for each value of the bias B. The computation of the identities of the neighbors by the nodes is performed using simple binary operations in parallel.     

Dynamic reconfiguration of node location in wormhole networks

Several techniques have been developed to increase the performance of parallel computers. Reconfigurable networks can be used as an alternative to increase the performance. Network reconfiguration can be carried out in different ways. Our research has focused on distributed memory systems with dynamic reconfiguration of node location. Briefly, this technique consists of positioning the processors in the network depending on the existing communication pattern among them, to suit the requirements of each computation.In this article, we present a dynamic reconfiguration technique for wormhole networks. We have used both a crossbar and a multistage interconnection network to implement a reconfigurable logical two-dimensional (2-D) torus topology. The reconfiguration mechanism is based on a distributed reconfiguration algorithm. The algorithm is based on a cost function that requires only local information. We discuss reconfiguration features and adjust the different parameters of the reconfiguration algorithm. We have also studied the deadlock problem in reconfigurable wormhole networks, and give details of our solution. Finally, we have evaluated the performance of this technique under several workloads.     

Real-time task scheduling and network device security for complex embedded systems based on deep learning networks

As a hotspot of machine learning research, deep learning is applied in many fields. Embedded systems are becoming more and more complex and networked, so the real-time performance of embedded systems and the security of network embedded devices face severe challenges. Based on this, this paper studies the real-time task scheduling problem for complex embedded systems and the security of embedded network devices. For real-time, this paper proposes a comprehensive task scheduling algorithm. Based on the task classification in the embedded system, different scheduling methods are adopted for different tasks, and the scheduling mode is flexibly changed as the system load changes. A dynamic integrity measurement model is established based on the star trust chain structure, and the hardware implementation mechanism of constructing dynamic trust chain in embedded system is studied. The dynamic reconfigurable hardware design method based on FPGA is applied to the construction of dynamic trust chain, and a verification system is designed to verify the dynamic measurement mechanism. This can solve the security problem of deep network embedded devices to a certain extent.     

支持动态互连的多处理器系统设计

针对多处理器系统通信带宽的高需求,结合LocalLink协议和Batcher-Banyan交换网络,提出一种适合在FPGA中实现的动态互连网络.与传统总线互连方式相比,该系统的通信性能有了较大的提高,仅占用少量硬件资源,便于集成新的通信接口,为多处理器系统设计提供了一种高性能且灵活的互连方式.     

基于MAS的动态生产调度与控制及系统开发

提出基于MAS的面向敏捷制造的生产过程动态调度与控制的层次结构．1）以任务分解与分配层为中心，建立各层之间的协调工作及协同决策机制；2）引入协商式招／投标方法实现任务的分解与分配；3）采用能力匹配与动态调度相结合的方法实现任务分配与调度控制的有效集成；4）面向生产任务需求动态确定Agent粒度、组建MAS模型；5）适应制造系统状态变化的需要，进行任务的动态重构．讨论基于MAS的采用分级递阶和并行处理相结合的自治组织结构和运作模式，以及利用与组织结构相对应的层次黑板结构实现各Agent之间信息与数据共享．在支持生产过程动态调度与控制基础设施建设的基础上，结合奏川机床集团有限公司车间生产实际，研究开发了基于MAS的车间动态调度系统．