m条对角线的n阶对角矩阵压缩存储的通用寻址公式

本文将通常数据结构中三对角矩阵压缩存储的寻址公式推广到ｍ对角矩阵（具有ｍ条对角线的ｎ（〉ｍ）阶矩阵）的情况，得到了新的一般寻址公式。同时指出文献「２」中关于这个问题所给出的公式是错误的。并用具体例子加以说明。     

主对角线两边非对称分布的带状稀疏矩阵的压缩存储通用寻址公式

本文研究一个数据结构的问题。将文献[1]中关于m-对角n阶矩阵的元素压缩存储的寻址公式推广到非对称情况,得到了另一种新的寻址公式。并用例子验证此公式的正确性。     

快速强隐式格式及其收敛性

§1.引言 在解线性代数方程组的许多迭代方法中,SIP(Strongly,Implicit procedure)是一个很好的方法,我们在[1,2,3]中列出了五条和七条对角线矩阵的几种格式,并讨论了它们的收敛性,本文在[1,2,3,8]的基础上,提出了五条和七条对角线矩阵的快速SIP格     

基于0-1属性矩阵的矩阵压缩存贮方法研究

在矩阵压缩存贮中引入0-1属性矩阵的概念,并在0-1矩阵的基础上给出了利用一维动态数组以及二维动态数组和一维动态数组混合存贮稀疏矩阵的寻址公式,该存贮方法为快速有效的存贮方法,节约了内存空间。     

对“按频率抽取的RBFFT算法”一文的修正

本文首先修正了“按频率抽取的RB FFT算法”一文中的错误,然后给出了RB FFT算法的另一个矩阵分解公式。按该公式进行计算所需运算量比按文[1]给出的两种都要少。     

内容寻址网络性能分析及优化

介绍了内容寻址网络的基本结构和工作原理,分析了内容寻址网络的3种基本操作：节点加入,节点失效以及寻路。该文从最大面积寻路、对角线寻路、层次化结构等3个方面提出了改进CAN寻路性能的措施,并通过仿真证实了这些措施对性能的改善。     

离散-连续混合系统输出公式——Mason公式的推广应用

本文用矩阵方程建立了离散-连续混合系统的数字模型,并由此推导出混合系统的输出公 式,该公式是Mason公式在混合系统中的推广.本文讨论了混合系统的另外两种解法,即矩 阵法和构图法. 本文结论与文献[3]有所不同.     

关于交换半环上一类矩阵的研究

对半环上可逆矩阵的概念进行推广,给出了[e]-可逆矩阵的定义。通过探讨可逆矩阵与[e]-可逆矩阵之间的内在联系,给出了交换半环上[e]-可逆矩阵的等价刻画。同时,对交换半环上[e]-可逆矩阵的全体关于矩阵乘法构成的半群进行研究,给出了此类矩阵半群的分解定理,并证明了此类矩阵半群均存在极大子群,且所有极大子群的并是Clifford半群。     

关于区间矩阵的稳定性

文献[1]试图给出由端点矩阵的稳定性来保证区间矩阵的稳定性,文[2,3]指出文[1]的主要结果是错的.本文给出了端点矩阵的稳定性在一定条件下可以保证区间矩阵的稳定性,其结果比文[4]更精确,适用范围更大,且对具有分解的区间矩阵给出了其稳定及不稳定的充分条件.     

任意矩阵的连接法中的简化规则

连接法的基本思想是证明矩阵中每一条路径都是互补的,即至少含有一个互补文字对,如果所有的路径是互补的则矩阵是互补的。因而原始待证公式是有效的,在[1]中W.Bibel给出了一阶逻辑的规范矩阵算法,这个算法容易推广到任意矩阵中。 作者在[2]中提出了几条应用于规范矩阵连接法的简化规则,本文提出两条可用于任意矩阵连接法的简化规则,它们的使用使得连接证明中要测试的路径和子目标的个数减少,并保证了原来矩阵的互补性。这两条规则作为定理来叙述并加以证明。     

Derivation of operational matrices of differentiation for orthogonal polynomials

A direct method for deriving an operational matrix of differentiation for Legendre polynomials is presented. The general case is also considered. The presented formulas are formally proved. Results are compared with the other known method. The new method is accurate for all matrix dimensions, while the other method may fail for higher dimensions.     

线性定常系统仿真的广义增广矩阵法

对于线性定常系统的数字仿真,增广矩阵法是一种高精度快速算法。本文给出了增广矩阵法的改进算法,由此建立了基于增广矩阵法的一般仿真模型。文中针对输入函数的不同情况给出了几种仿真计算模型。容易推证,原有的增广矩阵法乃是以本文算法给出的仿真计算模型之一的一种特例。     

Superposition laws for solutions of differential matrix Riccati equations arising in control theory

Representation formulas are given for the general solution of theN times Nmatrix Riccati equationdot{W} = A + WB + CW + WDWusingnknown solutions, withn = 1, ..., 5(n-representations). The 5- representation is a superposition formula, in that it expresses the general solution explicitly as a function of five particular solutions and N²arbitrary constants (N geq 2), using no further information. The representation formulas can be used in numerical calculations. The 4- and 5- representations are specially useful when a solutionW(t)has a singularity for some finitet = t_{0}. They also clarify the properties of the solution space: the matrix elements ofW(t)are meromorphic functions ofthaving simple poles as the only possible singularities. The relation between the representation formulas and previously known results is discussed.     

A new approach to matrix Heaviside expansion†

This paper presents a new procedure for the general matrix Heaviside expansion. The transfer matrix to be expanded can have many eigenvalues, each of which can have any multiplicity. The derivations of the formulas are based on Krylov' matrix and Vandermonde's transformation, and take advantage of using the particular nature of the inverse Jordan matrix. The results are extremely simple.     

Synchronizing the IEEE 1149.1 test access port for chip leveltestability

IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard's TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chip's scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard's basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features     

关于酉对称矩阵的QR分解的注记

研究了行(列)酉对称矩阵的性质,修正了行(列)酉对称矩阵的QR分解的公式和快速算法.结果可减少行(列)酉对称矩阵的QR分解的计算量与存储量,并且不会丧失数值精度.