动态二进制翻译中的指令调度技术研究与实现

动态二进制翻译提供了无需重新编译源代码就能将源机器生成的可执行代码自动转换到目标机器的方法,很好地解决了代码兼容性问题.其核心思想是根据程序的动态运行信息找到反复执行的代码序列,对代码序列进行翻译和优化,并将结果多次重用.指令调度作为一种有效的编译优化手段,也适用于动态二进制翻译.在对gcc的指令调度器分析研究的基础上,结合动态二进制翻译的实时性特点,提出了适合动态二进制翻译的效率高、开销小的指令调度算法.     

注解信息制导的动态二进制翻译及优化

动态二进制翻译器在运行时将源体系结构机器码翻译为目标体系结构机器码.这种即时编译技术使得源机器上的软件无需重编译就可以直接在目标机上较高效地运行.然而,利用动态二进制翻译器运行源软件的效率大大低于针对目标机器重新编译运行源软件的效率.本文在比较分析动态翻译生成的目的机器码的性能偏低的原因的基础上,提出了注解信息制导的动态二进制翻译及优化的方法.本文选取了三种注解信息,在英特尔的商用动态二进制翻译器"IA-32Execution Layer"和静态编译器"Intel(r)Compiler"上实现了注解信息制导的动态二进制编译及优化技术.实验结果表明该三种注解信息较大程度地提高了动态翻译码的执行效率.     

动态二进制翻译与优化技术研究

动态二进制翻译技术是一种即时编译技术,它将针对源体系结构编译生成的二进制代码(源机器码)动态翻译为可以在目的体系结构上运行的代码(翻译码).动态优化技术是指在运行时获取动态信息并进行代码优化的技术.动态二进制翻译及优化系统使得源软件无需重编译就可以直接在目标体系结构上高效地运行.目前几种比较有影响的动态二进制翻译及优化系统有Intel公司的IA-32 Execution Layer,IBM公司的DAISY,Transmeta的CMS及HP的Dynamo等.这些系统对动态二进制翻译系统关键技术有不同的实现.对动态二进制翻译和优化技术的研究是计算机领域的研究热点,具有深远的现实意义和应用前景.     

基于热例程的动态二进制翻译优化

依据对系统级程序行为特性的观察,提出了一种基于热例程的动态二进制翻译优化方法。该方法以频繁执行的例程作为优化单位,通过块内和块间优化算法消除动态二进制翻译引入的冗余。相比基于踪迹的优化方法,该方法具有优化单位发现开销更小、代码区域更大、无重复翻译等优点,更适用于系统虚拟机中操作系统代码的优化。在跨平台系统虚拟机监控器ARCH-BRIDGE上的测试表明,通过对内核代码实施该优化方法,SPEC CPUINT 2006程序的效率提升了3.5%~14.4%,相比基于踪迹的优化,性能最大提升了5.1%。     

动态二进制翻译中数据预取优化研究*

动态优化是动态二进制翻译研究中一个十分重要的课题,数据预取优化能提高现代处理器体系结构应用程序性能。基于超级块(Superblock)的动态数据预取优化采用软件插桩方式收集应用程序的load访存延迟信息并构造Superblock;然后根据延迟信息以及Superblock数据流分析得出的寄存器定值引用关系,对延迟load指令进行预取优化。通过在龙芯DigitalBridge动态二进制翻译系统上实验验证,数据预取优化可以提高翻译后SPEC2000浮点测试程序代码的平均性能3.3%,开销远小于0.5%。     

动态二进制翻译中全寄存器直接映射方法

二进制翻译是不同体系结构之间软件移植的重要手段。体系结构和硬件环境上的差别,可以通过二进制翻译系统来弥补,在翻译过程中往往使用多条本地指令模拟一条目标指令,翻译代码规模随之显著增加,从而导致被翻译程序的执行效率下降。寄存器作为处理器和内存交换信息的重要存储部件,寄存器的模拟器方式对于程序的性能有着至关重要的影响。为了提高特定平台翻译后代码的执行效率,提出了在动态二进制翻译机制中使用全部寄存器直接映射方法,详细分析了二进制翻译中的上下文切换原理和寄存器访问范围,为异构平台之间寄存器直接映射提供方法指导。利用QEMU模拟器,把x86架构的8个通用寄存器全部的直接映射到MIPS架构的对应寄存器,在此基础上,进行大量的指令翻译规则的简化。实验数据表明,该方法可以有效简化指令翻译,降低代码膨胀率,使得SPEC CINT 2000测试程序在龙芯CPU上翻译后代码运行时间下降了30%-40%。     

基于动态二进制翻译技术的仿真器研究

以动态二进制仿真器QEMU为平台,分析动态二进制翻译技术在仿真器开发中的应用,研究QEMU的翻译机制、优化策略、关键技术,并对相关重要代码进行解析。对仿真CPU的性能进行测试,结合分阶段的测试结果,从中找出制约仿真CPU性能的关键阶段,为后续的优化工作提供参考依据。     

动态二进制翻译中的TCache替换算法

动态二进制翻译中常常使用TCache来管理翻译优化后的代码,一个好的TCache管理策略可以大大提高程序的执行速度.讨论了动态二进制翻译系统的TCache的特性,介绍了一些已经被广泛使用的TCache替换算法,包括全清空,先进先出,以及由此发展而来的基于工作集的全清空,粗粒度的先进先出等.对它们各自的优缺点进行了比较,发现粒度适中的粗粒度的先进先出算法的综合性能最好,结合了全清空和先进先出的优点.     

基于龙芯处理器的二进制翻译器优化

二进制翻译是实现系统迁移的主要方法,但基于通用平台的仅靠软件实现的二进制翻译性能不高。该文以龙芯2F处理器为实现平台,提出一种QEMU二进制翻译器并进行优化,其中包括编译环境的优化以及二进制翻译器本身的优化2个方面,对后者的优化主要涉及寄存器直接映射和多媒体指令的改进。实验结果表明,通过寄存器映射优化后,系统能够获得1．45的加速比,通过多媒体优化后,多媒体程序的执行能达到本地机器执行的80％的性能。     

动态二进制翻译的库函数包装自动化

库函数包装是在动态二进制翻译过程中将源二进制程序的库函数调用直接转嫁到目标机上的库函数调用,以此提高动态二进制翻译系统的性能。针对目前动主流的库函数手动包装技术,提出一种基于GCC的动态二进制翻译中库函数的自动包装技术,无需对库函数分别进行人工包装,节省了大量的工作,同时也降低了包装过程中出错的可能性。实验结果表明,通过库函数自动包装技术,动态二进制翻译器qemu的性能有了3%~5%的提升。     

Automatic validation for binary translation

Binary translation is an important technique for porting programs as it allows binary code for one platform to execute on another. It is widely used in virtual machines and emulators. However, implementing a correct (and efficient) binary translator is still very challenging because many delicate details must be handled smartly. Manually identifying mistranslated instructions in an application program is difficult, especially when the application is large. Therefore, automatic validation tools are needed urgently to uncover hidden problems in a binary translator. We developed a new validation tool for binary translators. In our validation tool, the original binary code and the translated binary code run simultaneously. Both versions of the binary code continuously send their architecture states and the stored values, which are the values stored into memory cells, to a third process, the validator. Since most mistranslated instructions will result in wrong architecture states during execution, our validator can catch most mistranslated instructions emitted by a binary translator by comparing the corresponding architecture states. Corresponding architecture states may differ due to (1) translation errors, (2) different (but correct) memory layouts, and (3) return values of certain system calls. The need to differentiate the three sources of differences makes comparing architecture states very difficult, if not impossible. In our validator, we take special care to make memory layouts exactly the same and make the corresponding system calls always return exactly the same values in the original and in the translated binaries. Therefore, any differences in the corresponding architecture states indicate mistranslated instructions emitted by the binary translator. Besides solving the architecture-state-comparison problems, we also propose several methods to speed up the automatic validation. The first is the validation-block method, which reduces the number of validations while keeping the accuracy of instruction-level validation. The second is quick validation, which provides extremely fast validation at the expense of less accurate error information. Our validator can be applied to different binary translators. In our experiment, the validator has successfully validated programs translated by static, dynamic, and hybrid binary translators.     

一个用户级动态二进制翻译系统的设计与实现

本文介绍了一个x86 Linux系统下动态二进制翻译系统的设计与实现，该系统将IA-32用户级整数代码翻译到一个RISC指令集并由模拟器执行目标代码；详细描述了该系统的总体组成、目标结构模拟器、代码翻译过程以及翻译过的代码的执行。     

Towards a multiple-ISA embedded system

In these days, every new added hardware feature must not change the underlying Instruction Set Architecture (ISA), in order to avoid adaptation or recompilation of existing code. Binary translation (BT) allows the execution of already compiled applications on different architectures. Therefore, it opens new possibilities for designers, previously tied to a specific ISA and all its legacy hardware issues. To overcome the BT inherent performance penalty, we propose a new mechanism based on a dynamic two-level binary translation system. While the first level is responsible for the BT de facto to an intermediate machine language, the second level optimizes the already translated instructions to be executed on the target architecture. The system is totally flexible: it supports the porting of radically different ISAs and the employment of different target architectures. This paper presents the first effort towards this direction: it translates code implemented in the x86 ISA to MIPS assembly (the intermediate language), which will be optimized by the target architecture: a dynamically reconfigurable array. We show that it is possible to maintain binary compatibility, with performance improvements and no energy losses, when compared to native execution.     

如何取得Strong ARM处理器CPU的详细信息

介绍Strong ARM处理器的寄存器及取得CPU类型、频率的过程;介绍在WINDOWS CE应用程序中,如何直接嵌入二进制机器指令,取得底层的寄存器中的容;介绍利用Strong ARM指令参考手册中对指令的说明把取得寄存器中数据的过程翻译成机器码;另外对从寄存器中读取CPU的类型信息、从地址端口取得CPU频率的值的过程进行了说明。     

静态二进制翻译中回调函数逆向恢复技术研究

回调函数的逆向恢复是静态二进制翻译的一个难点。针对使用C后端的静态二进制翻译框架,提出并实现回调函数逆向恢复方法,该方法结合代码间隙分析,在后端C代码生成过程中插入映射源回调函数地址到目标机函数地址的代码。相对于使用解释器的方法,该方法具有实现简洁,在目标机上运行速度更快的优点。     

A Tree-Based Alternative to Java Byte-Codes

Despite the apparent success of the Java Virtual Machine, its lackluster performance makes it ill-suited for many speed-critical applications. Although the latest just-in-time compilers and dedicated Java processors try to remedy this situation, optimized code compiled directly from a C program source is still considerably faster than software transported via Java byte-codes. This is true even if the Java byte-codes are subsequently further translated into native code. In this paper, we claim that these performance penalties are not a necessary consequence of machine-independence, but related to Java's particular intermediate representation and runtime architecture. We have constructed a prototype and are further developing a software transportability scheme founded on a tree-based alternative to Java byte-codes. This tree-based intermediate representation is not only twice as compact as Java byte-codes, but also contains more high-level information, some of which is critical for advanced code optimizations. Our architecture not only provides on-the-fly code generation from this intermediate representation, but also continuous re-optimization of the existing code-base by a low-priority background process. The re-optimization process is guided by up-to-the-minute profiling data, leading to superior runtime performance.     

系统级动态二进制翻译中的代码Cache索引

针对系统级二进制翻译中多地址空间共存的情况,提出2种使用虚拟地址和物理地址对代码Cache进行索引的方法。物理地址索引方法有助于各个进程共享已被翻译的代码Cache。测试结果表明,在多进程环境下,物理地址索引的性能高于虚拟地址索引。     

轻量级嵌入式软件动态二进制插桩算法

软件二进制插桩是软件性能分析、漏洞挖掘、质量评价领域的关键技术。在嵌入式环境下,传统动态插桩算法受到无操作系统、CPU架构复杂、内存资源紧张等局限,难以展开工作。文章以软件动态二进制插桩算法为研究目的,通过静态特征分析和动态跟踪算法,引入图论算法对固件中的二进制进行分析,提出了嵌入式设备远程调试协议,实现了对软件运行时信息的获取。与传统方案相比,文章所想方案解决了现有工具对源码、操作系统或CPU架构的依赖,同时显著降低了内存和运算资源的占用率,可以有效解决嵌入式设备的动态插桩问题。