High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

In this paper, high-throughput and flexible hardware implementations of the SIMON and SPECK lightweight block ciphers are presented. The most complex block in the SPECK algorithm is addition modulo 2ⁿ, where n is word size (half of the input data). In the proposed structure of modular adder, we used the Sklansky adder, which is an efficient parallel prefix adder with low critical path delay and suitable hardware resources. In the SIMON block cipher, to reduce critical path delay, we use a tree structure for implementation of XOR operations. In addition, we proposed flexible structures that can perform various configurations of the SIMON and SPECK ciphers to support variable key sizes (128, 144, 192, and 256 bits) and block sizes (64, 96, and 128 bits). Therefore, the flexible architectures provide versatile implementations with adaptive security level and the ability of encryption of longer messages based on variable key size and variable block size. Implementation results of the proposed structures in 180 nm CMOS technology for different key and block sizes are achieved. The results show that the proposed structures have better critical path delay compared with other's related works.     

Optimal design of symmetric fractional delay filter using firefly algorithm

A fractional delay filter is used to increase the accuracy, preciseness, time synchronization, and stability of signal processing system. However, designing a fractional delay filter for a specified delay, without affecting spectral characteristics of the signal is challenging because of nondifferentiability and multimodal nature of its objective function. In this paper, a more accurate design technique has been proposed for designing fractional delay filters, based on a recently developed firefly algorithm and its improved version. The designed filters offer variable fractional delay. A novel symmetric structure of implementation has been used to design filters. The efficacy of the proposed technique is evaluated by considering a filter design example. The performance of the proposed technique is compared with the other exiting algorithm. The comparative analysis of finite impulse response (FIR) fractional delay filter design proves that the proposed algorithm has a smaller design error and an implementation complexity than the other reported existing algorithms. In addition to this, the designed FIR fractional delay filter is implemented on Xilinx Virtex-7 for experimental validation.     

Block parallel processing of 2-D digital signals

A structure is presented for the processing of two-dimensional digital signals, based on a block state-space model. Specifically the proposed structure exhibits high inherent parallelism since the state-space model is properly split into a number of parallel subfilters. A detailed analysis is done to achieve a balanced distribution of the necessary non-trivial multiplications in the subfilters. The optimal block dimensions are determined in order to minimize the critical number of non-trivial multiplications per output sample. Finally an estimation of the data throughput delay, based on the number of necessary multiplications and additions, is given for the proposed structure. It is shown that the data throughput delay, estimated in the case of optimal block dimensions, is increased almost linearly with the filter's order and is substantially reduced relative to that which has been estimated with the canonical state-space model. Also the data throughput delay for suboptimal block dimensions are considered. The proposed model is ideally suited to computer use and VLSI implementation.     

Security research with Square attack to a variant Camellia cipher

This paper investigates the relation between the choice of S-boxes and Square attack. A variant Camellia, which uses only a single S-box instead of four, is proposed. The security of the variant Camellia against Square attack is studied in detail. Result shows that it needs only 28 chosen plaintexts to recover a byte of the 6th round-key of variant Camellias, while the original Camellia needs either 28 chosen plaintexts to recover a byte of the 6th round-key and a byte of some constant or 216 chosen plaintexts to recover a byte of the 6th round-key. Furthermore, Square attacks on other round-reduced variant Camellia are proposed, and the time complexity of 11-round attack is reduced from 2²⁵⁰ to 2^225.5. The weaker variant Camellia indicates that the choice of S-box and the order of different S-boxes have influence on Square attack.     

System level design and analysis of a fourth‐order continuous‐time delta‐sigma modulator using relaxed gain‐band‐width amplifiers

In this paper, based on mathematical approaches and behavioral modeling of internal blocks, an algorithm of designing a continuous‐time delta‐sigma modulator (CT ΔΣM) with aggressive noise shaping is discussed. Using proposed methods, the coefficients of modulator can be calculated directly while the finite gain‐band‐width of amplifiers and rise/fall time of digital‐to‐analog convertors (DACs) in feedback path are included in the transfer function of CT loop filter. To decrease the number of amplifiers, a unique resonator is proposed. Also, an extra feedback DAC is introduced to further reduction of gain‐band‐width requirement of last amplifier. To verify the effectiveness of proposed methods, a fourth‐order, single loop, CT ΔΣM that benefits proportional‐integrator element for compensation of excess‐loop‐delay is realized in system and behavioral circuit levels. It has a 4‐bit quantizer, over‐sampling‐ratio of 10, and out‐of‐band‐gain of 12 dB. The peaking in signal‐transfer‐function is alleviated using a feed‐forward capacitor along with proper choosing of rest coefficients. The designed modulator has 78‐dB signal‐to‐noise‐ratio; even the non‐ideal behaviors of amplifiers and DACs are involved in simulations. Independent to sampling frequency, the proposed methods can be applied to other topologies of CT ΔΣMs. Copyright © 2017 John Wiley & Sons, Ltd.     

基于布尔可满足性的层次化通路时延故障测试

针对现代VLSI电路趋向于层次化的设计,本文提出了基于布尔可满足性的层次化通路时延故障测试方法,采用面向模块级的增量布尔可满足性合取范式的提取,从高到低层次化实现了关键通路的判别及子式生成.利用电路的时延测试条件蕴涵并转化为相应的约束子句,有利于将冲突尽早提前,以减少搜索空间.通过将已有的判别模块储存起来,作为学习子句,避免重复判别,极大的加快了子式的提取且降低了求解的规模和难度.仿真结果表明本文方案具有测试时间短、效率高,特别适合于具有模块化、规则化结构的层次化设计电路.     

A new fast‐lock,low‐jitter,and all‐digital frequency synthesizer for DVB‐T receivers

Lock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and f_REF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright © 2013 John Wiley & Sons, Ltd.     

An efficient small‐delay faults simulator based on critical path tracing

Testing for small‐delay defects (SDDs) has become an important component of integrated circuit testing. In this paper, an efficient small‐delay fault simulator, a hybrid method combining forward serial simulation and backward critical path tracing simulation for SDDs is proposed, which aims to determine the coverage of small‐delay defects for a given test set fast and accurately. In our proposed method, a unit delay model is employed, and reconvergent sensitization as well as hazard‐based detection is considered. Signal waveforms are expressed by bitmap data forms. In addition to providing an accurate result for fault simulation, the proposed simulator can well assist test generation. Experimental results demonstrate that the proposed simulator can further accelerate the simulation by one or two orders of magnitude compared with previous works. Copyright © 2014 John Wiley & Sons, Ltd.     

Greedy approach to sparse multi‐path channel estimation using sensing dictionary

As most components of sparse multi‐path channel (SMPC) are zero, impulse response of SMPC can be recovered from a short training sequence. Although the ordinary orthogonal matching pursuit (OMP) algorithm provides a very fast implementation of SMPC estimation, it suffers from inter‐atom interference (IAI), especially in the case of SMPC with a large delay spread and a short training sequence. In this paper, an adaptive IAI mitigation method is proposed to improve the performance of SMPC estimation based on a general OMP algorithm. Unlike the ordinary OMP algorithm, a sensing dictionary is designed adaptively and posterior information is utilized efficiently to prevent false atoms from being selected due to serious IAI. Numeral experiments illustrate that the proposed general OMP algorithm based on adaptive IAI mitigation outperforms both the ordinary OMP algorithm and the general OMP algorithm based on non‐adaptive IAI mitigation. Copyright © 2011 John Wiley & Sons, Ltd.     

A Low-cost Reconfigurable Field-programmable Gate Array Based Three-phase Shunt Active Power Filter for Current Harmonic Elimination and Power Factor Constraints

Non-linear loads, such as switched mode power supply, adjustable-speed drives, arc furnaces, etc., result in deterioration of power quality in terms of current harmonics and reactive power demand. Shunt active power filters are widely used to compensate the current harmonics, thereby improving power quality. Digital signal processors and microcontroller units used in digital control of shunt active power filters are constrained by a complex algorithm structure, adaptability, accuracy, the absence of feedback loop delays, and larger execution time. Shunt active power filters require a faster computation update rate to maintain the closed-loop bandwidth, accurate sensing of voltage and current, proper estimation of parameters, and a high frequency pulse-width modulation. In this article, a low-cost single all-on-chip field-programmable gate array implements the digital control of a three-phase shunt active power filter. This proposed implementation scheme has much less execution time and boosts the overall performance of the system. All required tasks of a typical shunt active power filter are implemented with a low-cost single all-on chip field-programmable gate array module that provides freedom to reconfigure for any other applications. Additional features, such as anti-windup, over-sampling, and time multiplexing, are also added to improve the overall performance. The proposed system is designed to meet IEEE 519 and IEC EN 61000-3 recommendations in terms of harmonic elimination and unity power factor requirements. The entire algorithm is coded, processed, and simulated using Xilinx 12.1 ISE Suite to estimate the advantages of the proposed system. This code is also defused on the low-cost single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype, and experimental results obtained match with simulated counterparts. The proposed control scheme for the shunt active power filter results in reduces current harmonics under dynamic and steady-state operating conditions.     

New simple transistor realizations of second- generation voltage conveyor

In this paper, two new complementary metal oxide semiconductor (CMOS) realizations for second-generation voltage conveyor (VCII) are presented. The first proposed VCII has a very simple structure employing only six transistors. The second proposed VCII employs 11 transistors, and none of the transistors at both proposed circuits suffer from the body effect. Small-signal analysis, parasitic elements, and input-referred noise of the proposed VCIIs are given. Moreover, a new active element called voltage controlled second-generation voltage conveyor (VC-VCII) is proposed as dual element of current controlled second-generation current conveyor (CCCII) active element. Its parasitic resistance at the Y terminal can be controlled electronically. Two presented CMOS structures of VCII are worked as VC-VCII with slight modification. Proposed circuits are simulated in Cadence Analog environment using TSMC 0.18-μm process parameters with ±0.9-V supply voltages. Both CMOS structures occupy a small chip area of 276.8 and 271 μm², respectively. The bandwidth of the current follower stage of the proposed VCIIs is found as 794 MHz, whereas the bandwidth of the voltage follower stage for the first and second proposed VCIIs is found as 2.57 and 1.92 GHz, respectively. As an application example, voltage-mode first-order low-pass filter has been given with its tunable gain by using VC-VCII.     

Secure data processing with massive‐parallel SIMD matrix for embedded SoC in digital‐convergence mobile devices

This paper presents secure data processing with a massive‐parallel single‐instruction multiple‐data (SIMD) matrix for embedded system‐on‐chip (SoC) in digital‐convergence mobile devices. Recent mobile devices are required to use private‐information‐secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the device's required specifications, especially cipher implementation for fast processing, power consumption, low hardware cost, adaptability, and end‐user's operation for maintaining the safety condition. To satisfy these security‐related requirements, we propose the interleaved‐bitslice processing method, which combines two processing concepts (bitslice processing and interleaved processing), for novel parallel block cipher processing with five confidentiality modes on mobile processors. Furthermore, we adopt a massive‐parallel SIMD matrix processor (MX‐1) for interleaved‐bitslice processing to verify the effectiveness of parallel block cipher implementation. As the implementation target from the Federal Information Processing Standardization‐approved block ciphers, a data encryption standard (DES), triple‐DES, and Advanced Encryption Standard (AES) algorithms are selected. For the AES algorithm, which is mainly studied in this paper, the MX‐1 implementation has up to 93% fewer clock cycles per byte than other conventional mobile processors. Additionally, the MX‐1 results are almost constant for all confidentiality modes. The practical‐use energy efficiency of parallel block cipher processing with the evaluation board for MX‐1 was found to be about 4.8 times higher than that of a BeagleBoard‐xM, which is a single‐board computer and uses the ARM Cortex‐A8 mobile processor. Furthermore, to improve the operation of a single‐bit logical function, we propose the development of a multi‐bit logical library for interleaved‐bitslice cipher processing with MX‐1. Thus, the number of clock cycles is the smallest among those reported in other related‐studies. Consequently, interleaved‐bitslice block cipher processing with five confidentiality modes on MX‐1 is effective for the implementation of parallel block cipher processing for several digital‐convergence mobile devices. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A measurement method for atmospheric ion mobilities based on cylindrical electrodes in direct current corona discharge

Ion mobility is one of fundamental parameters to describe the motion of ions in an electric field and a significant quantity to calculate the ionized field and ion current density of ultrahigh‐voltage direct current (UHVDC) power lines. This paper presents a measurement method for atmospheric ion mobilities in a DC corona discharge. An apparatus with coaxial cylindrical electrodes is designed and utilized. A vibrating electric field meter is employed to measure the ionized field of the electrode. Experimental results show that under atmospheric conditions, the average positive and negative ion mobilities are 1.76 × 10⁻⁴ and 1.88 × 10⁻⁴m²·V⁻¹·s⁻¹, respectively. The proposed method is compared with previous works of others. The impact of fluctuations of the measured ionized field and ion current density on the results of ion mobilities is also analyzed. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of novel efficient adder and subtractor for quantum‐dot cellular automata

Quantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the implementation of these designs may lead to the efficient use of the calculative unit in various applications, which may be used as a basic building block of a general purpose nanoprocessor. Copyright © 2014 John Wiley & Sons, Ltd.     

FPGA implementation of a coupled‐map‐lattice‐based cryptosystem

In this paper, a multimedia cryptosystem is first proposed and then implemented by a field programmable gate array (FPGA). A stream cipher is designed for the cryptosystem based on a coupled map lattice (CML), which can exhibit extremely complex spatiotemporal chaos. To improve the encryption speed, it is digitized and implemented in the FPGA. A user‐friendly interface is designed for users to input data from a PC, to manipulate the cryptosystem to encrypt/decryt and to observe the results. The data communication between a user's PC and the FPGA is realized via an enhance parallel port. The performance of the cryptosystem, i.e. statistical properties, security and speed, are quantitatively analyzed to be satisfactory. Further, the effectiveness of applying the cryptosystem in a text file, an audio file and an image file is verified by investigating the distributions and correlations of a plain‐media (i.e. plain‐text, plain‐audio or plain‐image) and its cipher‐media (i.e. cipher‐text, cipher‐audio or cipher‐image), and the diffusion with respect to a plain‐media. It is shown that the cryptosystem has high security, high speed, low cost and easy‐to‐use property, and can be widely applied for encrypting multimedia. Copyright © 2008 John Wiley & Sons, Ltd.     

考虑通信约束的区域保护分区策略及其实现技术

基于区域电网多源信息的区域保护依赖于通信技术和通信基础,实现广域大电网分区域保护必须着眼于考虑通信约束的分区策略与实现。基于此目的,考虑对子站与主站通信影响最大的跳数因素,并结合分区域的均衡性,基于Floyd最短路径算法提出一种排列组合择优法的区域保护主站选取模型;进一步根据区域性保护通信时延的影响因素指标建立子站划分模型。针对分区域形成后发生N-1信道故障的情况,分析其子站通信迂回过程,考虑通信延时的影响对分区域策略进行修正。最后,基于图论技术提出了分区域策略的实现技术与方法。     

A wide range delay locked loop for low power and low jitter applications

In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.     

Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS

In this work, a robust, low-power, widely linear multiphase clock generation and multiplying delay-locked loop (MPCG-MDLL) architecture is realized, using a new differential charge-mode delay element circuit topology. The heart of any MPCG-MDLL architecture is the delay element, and hence, the characteristics of the delay element influence the overall performance of the MPCG-MDLL, in terms of its specifications such as peak-to-peak jitter, lock range, delay range, control voltage range, and power consumption. The proposed eight-phase MPCG-MDLL along with the charge-mode delay element outperforms the conventional MPCG-MDLLs that deploy delay elements such as a current-starved inverter (CSI), wide-range CSI, triply controlled delay cell, digital-controlled delay element, and the like. The eight-phase MPCG-MDLL along with the new charge-mode delay element circuit topology is implemented in 1.2-V, 65-nm CMOS technology. The performance results show that the eight-stage delay line has a delay range from 640 to 960 ps over the rail-to-rail control voltage range. The implemented MPCG-DLL is robust over process, voltage, and temperature (PVT) corners and exhibits a lock range of 400 MHz and a peak-to-peak jitter of less than 60 fs for all the DLL output phases and peak-to-peak jitter of 0.54 and 1.24 ps for the synthesized 5-GHz clocks for an input reference clock frequency of 1.25 GHz. The MPCG-MDLL consumes 4.74 mW of power and occupies an area of 0.017 mm².     

极端灾害下考虑应急转供的配网停电过程仿真方法

提出了新的灾害下配电网故障模拟方法,其中综合考虑了台风灾害对设备运行可靠性影响以及关键负荷最优应急转供策略执行效果。首先,对极端灾害进行时空建模,评估受灾配电网元件和关联馈线停运概率;其次,分析关键负荷复电最优转供路径,形成应急供电拓扑;进一步,设计时序蒙特卡洛仿真流程,模拟气象条件、设备停运和应急转供等不确定因素影响下配电网停电随机动态过程。最后,采用IEEE算例构建灾害场景,证明了所提仿真方法的有效性和实用性。     

谐波相量测量的FIR滤波算法

为实现广域范围内谐波相量监测,需要研究与谐波相量功能相适应的测量算法。参照同步相量测量P类要求,研究长度为2周波有限冲激响应(finite impulse response,FIR)带通滤波器,实现各次谐波同步相量快速准确测量。通过研究滤波器频响特性与频偏条件下由基波、被测谐波、干扰谐波和宽带噪声引起测量误差之间定量关系,定义多项滤波器技术指标,根据误差要求制定滤波器设计准则,并由动态谐波相量虚指数函数模型和加权最小二乘算法实现滤波器的具体设计。仿真试验验证了所设计算法在系统稳态和动态条件下性能良好。