A second-generation voltage conveyor (VCII)–based simulated grounded inductor

In this paper, an implementation of a simulated grounded inductor (SGI) based on a recently developed active building block called second-generation voltage conveyor (VCII) is proposed. The proposed SGI employs two VCIIs, two resistors, and one grounded capacitor, which is preferred when integration is involved. More importantly, unlike most of the other previously reported SGIs, this one is free from any restrictive matching conditions. A complete analysis of nonidealities along with sensitivity treatment by considering parasitic impedances and nonideal gains of the VCII are performed. A simple VCII circuit is designed to be used in the implementation of the proposed SGI. To support the presented theory, Pspice simulation results using 0.18-μm CMOS technology parameters and supply voltage of ±0.9 V are provided. On the basis of the achieved results, the proposed SGI operates in a good agreement with an ideal inductor. The power consumption is only 0.65 mW, and the parasitic series impedance is approximately 191.9 Ω. The applicability of the proposed SGI is tested by using it in a standard second-order high-pass RLC filter.     

Current/voltage mode full-wave rectifier based on a single CCCII

A novel full-wave rectifier (or inverting full-wave rectifier) based on a single second-generation current controlled conveyor (CCCII) having no external passive components and diodes, conducive to IC implementation, is proposed in this paper. The circuits are capable of precisely processing the input signals of up to 30 MHz frequency, while in the situation when the circuits are operating in a voltage mode (VM), the allowed range of possible changes in the input voltage signal is ±500 mV compared with ±1 mA in the current mode (CM). In order to more fully perceive the performance of the proposed full-wave rectifier, the influence of nonidealities and parasitic impedances effects on its work was analyzed. The simulation results using 0.35-μm parameters confirm the feasibility of the proposed solutions.     

Realizations of fully differential voltage second generation current conveyor with an application

Three novel CMOS realizations for the fully differential voltage second‐generation inverting current conveyor (FDVCCII‐) are proposed in this paper. The first realization has a limited input range, and the other two realizations have a rail to rail input range and show excellent features in linearity and bandwidth. As an application to the FDVCCII‐, a floating gyrator is proposed. A floating inductor is realized using the floating gyrator and it is used in realizing a second‐order low‐pass filter, which is simulated and compared with the ideal result. All circuits are simulated with SPICE using CMOS 0.35µm technology and supply voltages ±1.5V to verify the theoretical results. Copyright © 2008 John Wiley & Sons, Ltd.     

A new differential configuration suitable for realization of high CMRR, all-pass/notch filters

In this paper, a new configuration suitable for realization of differential input-differential output first order, second order all-pass and notch filters with high CMRR is given. The proposed configuration uses two negative type second-generation current conveyors (CCII-), and three admittances. Two first order and one second order all-pass filters and a notch filter (tunable if current controlled conveyor CCCII is used) are extracted from the proposed configuration. Tracking error, element mismatch, sensitivity analysis, simulation and experimental results are included.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

A novel dual output universal filter topology using a single current conveyor

In this paper, a new voltage mode universal filter topology is presented. The proposed topology can provide three circuits with all-pass, notch, band-pass, low-pass and high-pass filtering functions employing minimum number of active and passive components, namely a single first generation current conveyor, two resistors and two capacitors. Furthermore, these circuits obtained from general topology have dual outputs that can be used simultaneously. Sensitivities of the pole frequency and quality factor of the filter to the passive components can be made lower than unity in magnitude. Finally, natural frequencies of the presented circuits are independent from non-ideal voltage gain of the active element. Simulations are performed to verify the theoretical results.     

A proposal for high‐performance CCII‐based analogue CMOS design

A novel fully differential CMOS second‐generation current conveyor (CCII) topology is presented. It can be considered as a universal fully differential programmable active element. The circuit operates in moderate inversion region, and features high linearity over a wide input range. Current gain between terminals X and Z can be continuously tuned in a wide range. These features are essential to extend the utilization of CCII‐based circuits to high‐performance VLSI applications. Analogue design based on this new cell is illustrated by various examples. The proposed CCII has been fabricated in a 0.5‐µm CMOS technology and its main performance characteristics have been measured. They are in good agreement with theory and demonstrate that operation in moderate inversion can lead to distortion levels much lower than those achieved in strong inversion. Experimental results for a Tow–Thomas biquadratic filter fabricated on the same chip are also presented, showing continuous frequency tuning in more than a decade. Copyright © 2005 John Wiley & Sons, Ltd.     

A 0.5 V bulk‐driven voltage follower/DC level shifter and its application in class AB output stage

A simple realization of a 0.5 V bulk‐driven voltage follower/direct current (DC) level shifter designed in a 0.18 µm CMOS technology is presented in the paper. The circuit is characterized by large input and output voltage swings and a DC voltage gain close to unity. The DC voltage shift between input and output terminals can be regulated in a certain interval around zero, by means of biasing current sinks. An application of the proposed voltage follower circuit for realization of a low‐voltage class AB output stage has also been described in the paper. Finally, the operational amplifier exploiting the proposed output stage has been presented and evaluated in detail. Copyright © 2014 John Wiley & Sons, Ltd.     

The CMOS differential stage with active load intuitively demonstrates the unequal split of the differential input Voltage

The authors propose a new intuitive demonstration-with the help of the Reductio ad Absurdum technique-of one "interesting" feature of the complementary metal-oxide-semiconductor (CMOS) differential stage with an active load, namely, unequal split of the differential input voltage (the gate-source voltage is not equal for the input transistors). This kind of demonstration is very useful for challenging the students' thinking and for developing a "sense" of electronic circuits operation.     

Digitally programmable second generation current conveyor‐based FPAA

A novel fully differential digitally programmable current conveyor (DPCCII) is presented in this paper. The programmability of the proposed DPCCII is achieved using three‐bit MOS R‐2R ladder current division network. The DPCCII is used to realize a field programmable analog array (FPAA). The FPAA consists of seven configurable analog blocks arranged in a hexagonal form. The FPAA power consumption is 72.3 mW from 1 V voltage supply. A second‐order programmable universal filter is realized using the proposed FPAA as an application. All the circuits are realized and simulated using 90 nm IBM CMOS technology model under balanced supply voltage of ±0.5 V. Copyright © 2012 John Wiley & Sons, Ltd.     

Second‐order intermodulation cancelation and conversion‐gain enhancement techniques for CMOS active mixers

In this paper, two new techniques are proposed to improve the second‐order input intercept point (IIP2) and conversion‐gain in double‐balanced Gilbert‐cell complementary metal‐oxide semiconductor (CMOS) mixers. The proposed IIP2 improvement technique is based on canceling the common‐mode second‐order intermodulation (IM2) component at the output current of the transconductance stage. Additionally, the conversion‐gain is improved by increasing the fundamental component of the transconductance stage output current and creating a negative capacitance to cancel the parasitic capacitors. Moreover, in the proposed IM2 cancelation technique, by decreasing the bias current of the switching transistors, the flicker noise of the mixer is reduced. The proposed mixer has been designed with input frequency and output bandwidth equal to 2.4 GHz and 20 MHz, respectively. Spectre‐RF simulation results show that the proposed techniques simultaneously improve IIP2 and conversion‐gain by approximately 23.2 and 5.7 dB, respectively, in comparison with the conventional mixer with the same power consumption. Also, the noise figure (NF) at 20 kHz, where the flicker noise is dominant, is reduced by 4.9 dB. The average NF is increased nearly 0.9 dB, and the value of third‐order input intercept point (IIP3) is decreased approximately 1.8 dB. Copyright © 2014 John Wiley & Sons, Ltd.     

On the input common‐mode voltage range of CMOS bulk‐driven input stages

In this paper the response of a bulk‐driven MOS Metal‐Oxide‐Semiconductor input stage over the input common‐mode voltage range is discussed and experimentally evaluated. In particular, the behavior of the effective input transconductance and the input current is studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35‐µm CMOS Complementary Metal‐Oxide‐Semiconductor technology, demonstrates that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source‐bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk‐driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5‐V second‐order operational transconductance amplifier (OTA)‐C lowpass filter. Experimental results validate the effectiveness of the approach. Copyright © 2010 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

High output impedance CMQOs using DVCCs and grounded components

In this paper a new circuit topology for realizing second‐order current‐mode quadrature oscillator is proposed. Three additional circuits are further derived from it, thus resulting in four distinct circuits. Each circuit employs three differential voltage current conveyors and all grounded passive components, ideal for IC implementation. All the circuits possess high output impedance. The circuits exhibit non‐interactive frequency control and low THD. The effects of non‐idealities are also analyzed. PSPICE simulations using 0.5 µCMOS parameters confirm the validity and practical utility of the proposed circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

Generation and classification of CCII and ICCII based negative impedance converter circuits using NAM expansion

A new simplified generation method of negative impedance converter circuits (NIC) is introduced. The generation method is based on nodal admittance matrix expansion starting from the input admittance of the NIC circuit terminated by a load rather than treating the NIC as a two‐port network element. The four pathological elements, namely nullator, norator, voltage mirror and current mirror, are used in the generation procedure. Two classes of the NIC pathological circuits are defined; each class includes two types. Eight pathological NIC circuits are generated for each class. Two alternative current conveyor and inverting current conveyor‐based realizations for each pathological circuit based on alternative pairing of the pathological elements are defined resulting in a total of 16 NIC circuit for each class and a total of 32 NIC circuits. A new NIC‐based circuits realizing floating negative impedances are also introduced. Copyright © 2010 John Wiley & Sons, Ltd.     

基于FGMOS的电压求和电流传送器及其应用设计

本文提出了一种基于FGMOS晶体管的电压求和电流传送器的设计。通过对FGMOS晶体管的等效电路分析,得到其框图和等效电路,并设计出了其电路结构;为了表明提出的电压求和电流传送器的可用性,将提出的电压求和电流传送器用于实现受控振荡器和电压求和放大器;通过SPICE的仿真结果表明,基于FGMOS的电压求和电流传送器不仅具有高的线性特性,而且其电压传递增益和电流传递增益分别可达0.99和0.98。此外,还有着很好的频率响应性能,?0.5V的低电源电压,79.8?W的低功耗和在14k?~2.1M?的线性电子可调谐电阻值。基于电压求和电流传送器设计的受控振荡器具有稳定的正弦输出,而且振荡频率值可以通过偏置电流来控制,设计的电压求和放大器具有高输入电阻和可控的增益。     

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.     

Current differential amplifiers: new circuits and applications

New CMOS current differential amplifiers are proposed suitable for analogue signal processing at high frequencies. They consist of simple current mirrors, which are easy to design and to implement in IC form. Low‐voltage low‐power design is feasible. Relying on these devices a number of applications are obtained, including lossy and lossless integrators, simulated inductors, active filters, and harmonic oscillators. Theoretical expressions are given for all of the proposed new circuits. The verification of the circuits is also achieved by simulation. Copyright 2001 © John Wiley & Sons, Ltd.     

The CCII+ and the ICCII as basic building blocks in low‐pass filter realizations

Three new grounded capacitor current mode low‐pass filters using two inverting second‐generation current conveyor (ICCII) or one double output ICCII are given. The circuits employ the minimum number of passive circuit components, namely two resistors and two capacitors. The circuits are generated from three new voltage mode low‐pass filters realized with the ICCII. A new grounded capacitor CCII+ current mode low‐pass filter is generated from one of the new voltage mode low‐pass filters employing two ICCII?. A new grounded passive component low‐pass filter with independent control on Q and using three ICCII+ is also introduced. Spice simulation results based on using the 0.5 µm CMOS model are included to support the theoretical analysis. Copyright © 2007 John Wiley & Sons, Ltd.