A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

A UWB receiver with modified CS-CG LNTA: Noise and nonlinearity analysis

A modified common source-common gate (CS-CG) low-noise transconductance amplifier (LNTA) with an improved noise figure (NF), operational bandwidth, and power consumption are analyzed in this paper. The common source (CS) stage of the modified LNTA is utilized for noise cancellation and transconductance enhancement of the common gate (CG) transistor. Using these, NF, bandwidth, and power consumption are improved without using extra active elements. Noise analyses show the modified CS-CG LNTA has lower NF than conventional CS-CG LNTA. The linearity of the modified CS-CG LNTA is calculated by Taylor series expression. Besides, a design procedure is proposed based on the obtained equations for linearity and NF. Finally, an ultra-wideband (UWB) surface acoustic wave (SAW-less) direct-conversion receiver is designed in 65 nm complementary metal-oxide-semiconductor (CMOS) technology. NF and third-order intercept point (IIP3) of the designed receiver are simulated as 5 dB and −2 dBm, respectively. The receiver consumes 18.4 mA from a 1.8 V supply voltage.     

Second‐order intermodulation cancelation and conversion‐gain enhancement techniques for CMOS active mixers

In this paper, two new techniques are proposed to improve the second‐order input intercept point (IIP2) and conversion‐gain in double‐balanced Gilbert‐cell complementary metal‐oxide semiconductor (CMOS) mixers. The proposed IIP2 improvement technique is based on canceling the common‐mode second‐order intermodulation (IM2) component at the output current of the transconductance stage. Additionally, the conversion‐gain is improved by increasing the fundamental component of the transconductance stage output current and creating a negative capacitance to cancel the parasitic capacitors. Moreover, in the proposed IM2 cancelation technique, by decreasing the bias current of the switching transistors, the flicker noise of the mixer is reduced. The proposed mixer has been designed with input frequency and output bandwidth equal to 2.4 GHz and 20 MHz, respectively. Spectre‐RF simulation results show that the proposed techniques simultaneously improve IIP2 and conversion‐gain by approximately 23.2 and 5.7 dB, respectively, in comparison with the conventional mixer with the same power consumption. Also, the noise figure (NF) at 20 kHz, where the flicker noise is dominant, is reduced by 4.9 dB. The average NF is increased nearly 0.9 dB, and the value of third‐order input intercept point (IIP3) is decreased approximately 1.8 dB. Copyright © 2014 John Wiley & Sons, Ltd.     

Fully integrated 2.45‐GHz OOK receiver for wireless sensor networks

This paper introduces an optimized receiver architecture using the current‐reuse technique to improve receiver sensitivity while minimizing power consumption. An ISM band wireless receiver with OOK modulation was implemented in the TSMC 0.18‐µm CMOS process. The receiver contains an RF front end, an LC‐tank based LO VCO, an IF amplifier and an OOK demodulator. In addition, the IF amplifier features a self‐mixing elimination mechanism which allows the BER to upgrade more than one order of magnitude. Measurement results show a sensitivity of ?63 dBm given a BER of 10^?3. Using the gain‐improving method, the sensitivity is improved by 4 dB (100‐kbps data rate). Including the bias circuit, overall power consumption is less than 383 μW under a 1.2‐V supply, providing an alternate solution for wireless radio applications. Copyright © 2016 John Wiley & Sons, Ltd.     

A novel low‐power receiver topology for RF and microwave applications

A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.     

Circuit and system design for an 860–960 MHz RFID reader front‐ends with Tx leakage suppression in 0.18 − µm CMOS technology

This paper presents an RF Front‐END for an 860–960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front‐end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front‐END contains a power amplifier (PA) in transmit chain and receive front‐end with low‐noise amplifier, up/down mixer, LP filter and variable‐gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18‐µm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power‐added efficiency of 24% with a power gain of 20 dB, including the losses of the bond‐wires. Copyright © 2011 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

Gain compression improvement on low‐power cascaded current reuse LNAs

Current reuse low‐noise‐amplifiers (CRLNAs) have been the norm to achieve high‐gain and low‐noise figure under low‐power budgets. However, conventional CRLNAs suffer from a severe lack of large‐signal linearity, especially in conventional cascaded CRLNAs. This main drawback is related with the typical biasing method imposed in the output stage. To prove our point, a large‐signal study is performed for a single stage common‐source in two distinct biasing situations: voltage biased and current biased. On the basis of the gathered results, a new CRLNA solution is proposed to relief the large‐signal bottleneck. The suggested design is analyzed in a 0.13 µm complementary metal–oxide–semiconductor (CMOS) standard process. Post‐layout simulations show 8 dB compression point improvement compared with the conventional CRLNA solution. The CRLNA draws a current of 650 μA from a 1.2 V supply. At 2.45 GHz, a power gain of 25.3 dB and a NF of 2.3 dB are achieved, while the IIP3 is ?9 dBm. Copyright © 2016 John Wiley & Sons, Ltd.     

360-μW 4.1-dB NF CMOS MedRadio receiver RF front-end with current-reuse Q-boosted resistive feedback LNA for biomedical IoT applications

In this paper, a low-power low-noise complementary metal-oxide semiconductor (CMOS) receiver RF front-end (RFFE) that employs a current-reuse Q-boosted resistive feedback low-noise amplifier (RFLNA) is proposed for 401 to 406 MHz medical device radio-communication service band IoT applications. By employing a series RLC input matching network, the proposed RFLNA has the advantages of both the conventional RFLNA and the inductively degenerated common-source LNA without using large on-chip spiral inductors at the sources of the main transistors. The proposed active mixer utilizes a current-reuse transconductor, in which a p-channel metal-oxide semiconductor (PMOS) transistor performs a current-bleeding function to reduce direct current (DC) and flicker noise in the switching stage of the active mixer. The proposed receiver RFFE is implemented in a 65-nm CMOS process and achieves a voltage gain of 30.9 dB, noise figure of 4.1 dB, S11 of less than −10 dB, and IIP3 of −22.9 dBm. It operates at a supply voltage of 1 V with bias currents of 360 μA. The active die area is 0.4 mm × 0.35 mm.     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

Low‐frequency noise analysis and minimization in Gilbert‐cell‐based mixers for direct‐conversion (zero‐IF) low‐power front‐ends

Low‐frequency (flicker) noise is one of the most important issues in the design of direct‐conversion zero‐IF front‐ends. Within the front‐end building blocks, the direct‐conversion mixer is critical in terms of flicker noise, since it performs the signal down‐conversion to baseband. This paper analyzes the main sources of low‐frequency noise in Gilbert‐cell‐based direct‐conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert‐cell‐based zero‐IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of ?10 dBm, which makes this mixer suitable for a multi‐standard low‐power zero‐IF front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

Design of 3.1 to 10.6 GHz ultra‐wideband flat gain LNA

In this paper, a new ultra‐wideband low‐noise amplifier (LNA) is proposed. The proposed LNA has flat gain and low noise figure (NF) in the frequency range of 3.1 to 10.6 GHz. To obtain higher gain, cascode architecture is used. In this design, to have a lower NF, the noise cancellation technique applies to the cascode architecture. In addition, to have better matching at the input and output, active feedback and matching transistors are used, which also leads to better NF. To have flat gain, RLC load is used. In the proposed LNA, only one inductor is used, which leads to the smaller chip area. The proposed circuit is designed in 90 nm CMOS technology. The simulation shows NF of between 1.62 and 2.1 dB, flat gain between 11.9 and 12 dB and power consumption of 11.72 mW in the frequency range of 3.1 to 10.6 GHz. The simulation results support the theoretical predictions. Copyright © 2017 John Wiley & Sons, Ltd.     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

A 1–6 GHz analog radio frequency power driver in 90 nm complementary metal‐oxide semiconductor technology for wireless applications

One of the most challenging subsystems for integrated radio frequency (RF) complementary metal‐oxide semiconductor (CMOS) solutions is the power amplifier. A 1–6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on‐chip RF signal chain components at ?12 dBm power levels and produces a 0 dBm signal to on‐chip or off‐chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi‐fingered transistors. The RF driver was fabricated as a stand‐alone sub‐circuit on a 90 nm CMOS die with other sub‐circuits. Experimental tests confirmed that the on‐chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third‐order intercept point (IIP3) were ?4.7 dBm and ?0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net‐lists. Copyright © 2013 John Wiley & Sons, Ltd.     

Design and analysis of 0.9 and 2.3-GHz concurrent dual-band CMOS LNA for mobile communication

A complementary metal-oxide-semiconductor (CMOS) dual-band low-noise amplifier (LNA) for 2G/3G/4G mobile communications is presented. It operates at 0.9 and 2.3 GHz of frequencies. The dual-band operation is achieved by adding a modified notch-filtering path in the wideband LNA. The modified notch-filtering path does not require additional power to cancel the signals of the stop band frequency. The impact of the filtering path in the proposed LNA is analyzed. Improved results are observed in dual bands of frequency. Sustainability of the LNA under process corner variation and temperature variation are examined, and it is found to be suitable for the application. The proposed LNA is designed at 90-nm technology in Cadence Virtuoso with 0.5 and 0.6-V supply. The post-layout simulation shows 22 dB of gain (S₂₁), 2 dB of Noise Figure (NF), and −5.5 dBm of IIP3 at the high band. In the low band, 24 dB of S₂₁, 2.7 dB of NF, and −6.65 dBm of IIP3 are reached. The circuit consumes 5.2 mW of power and 0.0918 mm² of area. The efficiency of the LNA is estimated by the figure of merit, and comparable results are secured in the proposed work.     

A 2- to 12-GHz 65-nm transmit/receive CMOS DP8T switching matrix for ultra-wideband antenna arrays

An ultra-wideband 2- to 12-GHz transmit/receive (T/R) double-pole–eight-throw (DP8T) switching matrix is developed with a 65-nm complementary metal oxide semiconductor (CMOS) process for a radar-based breast cancer detection system. The measured average insertion losses are 5.2, 7, and 10.6 dB at 2, 6, and 12 GHz, respectively, with input and output matching bandwidths of 2 to 12 GHz and a third-order input intercept point (IIP3) of 31 dBm at 8 GHz. The power consumption is less than 1 mW for a 1.2-V power supply. To the best of the authors' knowledge, this is the first reported DP8T CMOS switching matrix to replace the conventional mechanical switch to control a portable radar antenna.     

Base coupled differential amplifier: a new topology for RF integrated LNA

A new topology of bipolar low noise amplifier (LNA) for RF applications, named base coupled differential (BCD), is presented. The proposed approach is compared by simulation against most classical topologies. The BCD configuration has the key advantage to join an integrated matching on a single‐ended input with a differential output. This is done by using down‐bond wiring, so that no integrated inductors are needed. The main advantages of this new topology are a drastic area reduction and an increased linearity range (or a reduced biasing current with the same linearity) together with a noise figure (NF) and voltage supply reduction. Particularly, the BCD LNA presented in this paper has been designed for 2.44GHz frequency operation. It is characterized by a NF of 1.93dB, a voltage gain (Av) of 19.5dB, an input impedance of 50Ωa third Input‐referred Intercept Point (IIP3) of ‐7.25dBm and a dissipated power (PD) equal to 19mW. Copyright © 2003 John Wiley & Sons, Ltd.     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.