基于体效应的SiC MOSFET器件栅极老化监测方法研究

长期以来,栅极老化一直是SiC MOSFET器件可靠性研究的关键,而偏置温度不稳定性则是栅极老化的重要现象。由于栅极老化的偏置温度不稳定性存在应力撤出后的恢复现象,如能在可靠性实验中快速、准确地监测SiC MOSFET器件的栅极老化变化量,对可靠性研究具有重要意义。因此,文中提出一种新的栅极老化监测方法。该方法以体效应下的阈值电压VTH(body)为基础,建立理论模型来描述VTH(body)和栅极老化之间的关系。提出在栅极电压开关过程中从体二极管电压–栅极电压曲线中得到VTH(body)的方法,并详细研究实验参数对VTH(body)的影响。此外,通过高温栅偏实验对VTH(body)的实用价值进行验证,并与栅极老化参数阈值电压VTH进行对比。实验结果证明,提出的新型栅极老化监测方法可以实现栅极老化的快速、准确及非恒温环境监测。     

基于开通di_(ds)/dt的SiC MOSFET模块结温提取研究

碳化硅(SiC)金属-氧化物半导体场效应管(MOSFET)以其优良的性能得到广泛关注,结温是一个关键指标,用于健康状况监测。这里基于状态监控的需要,提出一种开通瞬态漏极电流变化率(di_(ds)/dt)结温提取的方法,首先从理论层面分析了di_(ds)/dt温度相关性,并用实验表明了di_(ds)/dt随着器件结温增加而增加,然后又对影响di_(ds)/dt的因素进行了分析,在双脉冲实验中证实了di_(ds)/dt的温度敏感度随负载电流和外部栅极电阻增加而增加,该方法在大驱动电阻下有更好的温度敏感度但也增加了开关损耗,牺牲了开关频率,基于此提出一种智能驱动器的方法,在不增加开关损耗的前提下有效测量SiC MOSFET的结温。     

基于Vth和Vce的IGBT结温测量方法对比研究

小电流下饱和压降法（Vce法）和阈值电压法（Vth法）是IGBT热阻测试标准中推荐使用的两种结温测量方法,然而并没有说明两种方法测得的结温的关系及等效性。首先理论分析了小电流下饱和电压和阈值电压的电压构成,表明Vce法测得的结温反映的是芯片集电极侧的温度信息,Vth法测得的结温反映的是芯片发射极侧的温度信息,由于芯片内部存在垂直温度梯度,推断Vth法测得的结温将高于Vce法测得的结温;然后根据两种测量方法的测量原理,搭建了IGBT结温测量平台,在不同负载电流下用两种方法测量结温,实验结果验证了理论预测,且两种方法测得的结温的差值随着负载电流增加而增大。最后,提出一种简易热校准模型用于快速计算差值,使得两种方法的结果可以等效变换并进行公平对比。     

恒流驱动下基于VeE＿max的IGBT模块解耦老化影响的结温测量方法

绝缘栅双极型晶体管（IGBT）的结温在线测量对于电力电子装置的安全可靠运行、延长使用寿命和热管理等都具有重要意义。然而,目前大多数温敏电参数均受IGBT模块疲劳老化的影响。为此,该文提出一种恒流驱动下基于感应电压峰值V_eE＿max的IGBT模块结温在线测量方法,该方法能够解耦键合线老化对温敏电参数的影响。基于双脉冲实验平台分析V_eE＿max的温线性度和温敏感度,并通过模拟键合线老化实验验证所提方法的老化解耦性。最后,通过Buck变换器验证该方法在运行变流器中在线结温测量的可行性。     

基于驱动电压调节的IGBT结温跟踪管控策略及实现

针对变流器在运行过程中由于频繁和大范围的随机出力变化,导致IGBT模块内部结温剧烈波动,影响器件运行可靠性的问题,提出并探讨了通过调节栅极驱动开通电压实现功率器件结温平滑跟踪管控策略的思想和具体实现方法。利用一种简化的IGBT损耗分析模型,阐述了驱动电压大小对IGBT损耗的影响,并通过双脉冲实验进行了验证。根据结温变化趋势的大小自动调节驱动电压,在不影响变流器输出性能的同时最大程度减少结温波动,并且具有较快的响应速度。构建了基于一种新型应力测试电路的结温跟踪管控实验平台,实验结果表明,该结温跟踪管控策略具有可行性和有效性,减小了器件承受的热应力冲击。     

一种基于门极电压阈值检测的SiC MOSFET结温在线监测方法

碳化硅(silicon carbide,SiC)金属–氧化物半导体场效应晶体管(metal-oxide-semiconductorfield-effect transistor,MOSFET)作为第三代功率器件的代表,已被广泛用于小容量高频领域,其可靠性问题备受关注。结温过高是制约SiC MOSFET可靠性的重要因素。然而,碳化硅器件高开关频率增大了动态参数测量的难度和成本。与硅基器件相比,其导通压降和导通电阻等稳态参数对结温的敏感性较低。因此,主流的热敏电参数法无法有效地在线监测结温。已有研究表明:门极阈值电压与结温密切相关,但这种通过门极阈值电压监测结温的方法易受电流震荡影响且测量电路复杂,故监测效果差强人意。为此,文中提出一种新型的基于门极电压阈值检测的SiC MOSFET结温监测方法。首先,理论推导结温与门极阈值电压之间的解析表达式,发现其呈线性关系。其次,提出一种多项式拟合门极阈值电压测量方法,并设计与之匹配的电流采样测量电路。最后,通过基于H桥单相逆变电路的在线监测试验证明该方法的有效性。研究表明:新型结温监测方法具有以下突出优势:1)不易受开关过程震荡的影响,监测精度高;2)测量电路简单可靠,仅用采样电路和滤波器即可,毋需复杂的捕捉电路;3)对采样频率具有一定的容差性。     

一种可提高IGBT可靠性的新型结温管控策略

变换器在运行过程中频繁和大范围地随机出力变化,会导致IGBT模块内部结温剧烈波动,使器件持续承受交变的热应力冲击,严重影响器件的可靠性。提出一种通过调节驱动电压实现功率器件结温平滑跟踪和自适应管控的策略。首先,基于简化的IGBT损耗分析模型,阐述了驱动电压大小对IGBT损耗的影响。然后,根据结温变化趋势的大小自动调节驱动电压,在不影响变流器输出性能的同时最大程度抑制结温波动,改善器件周期热应力,提高器件运行可靠性和寿命。最后,通过一种新型应力测试电路的结温跟踪管控实验平台进行实验测试,证明了该结温跟踪管控策略具有可行性和有效性。     

多数据驱动人工神经网络的 IGBT 结温在线估计方法

传统结温估计方法因其无法根据 IGBT 模块健康状态实时调校,从而导致当模块发生封装退化后无法准确估计结温。 因此,为解决在实际工况中模块封装退化造成的结温估计误差问题,建立了一个基于多数据驱动的以人工神经网络为主体的 IGBT 结温在线估计模型。 首先,确定饱和压降作为温敏电参数并研究其构成,分析其与集电极电流,芯片结温和封装退化之间 的耦合关系。 随后,为解决封装退化造成的饱和压降温度特性变化问题,提出结合米勒电压温度特性的优势,配合饱和压降与 集电极电流驱动人工神经网络算法构建结温估计模型,并通过搭建实验平台提取数据,完成模型的训练。 最终,通过与传统结 温估计方法对比估计误差,新模型将结温估计误差从 20%降低到了 5%以下。     

基于开通密勒平台电压的IGBT模块结温估计研究

已有研究表明,绝缘栅双极性晶体管(insulated gate bipolar transistor,IGBT)的可靠性与结温波动密切相关,如能准确地实时测量IGBT的结温,对可靠性的研究具有重要意义。依据温敏电参数法,该文提出一种基于栅极电压开通密勒平台的结温估计方法。首先分析IGBT栅极寄生电容的物理特性与温度的关系,得到栅极开通过程中密勒平台电压与结温线性相关;然后提出采用恒流驱动电路延长栅极电压开通过程中密勒平台持续时间,使其温敏感度与温线性度更高,可拟合出密勒平台值和结温间的线性关系;最后采用该方法对IGBT模块的结温估算进行实验验证,并与采用红外测温仪实时测量的结温进行对比,验证了所提方法的可行性和准确性。     

大功率IGBT模块结温提取研究

为了提高大功率功率变换器的可靠性,需要对大功率绝缘栅双极型晶体管(Insulated gate bipolar transistor,IGBT)模块进行温度监测,到目前为止,该领域对高压IGBT的研究很少。本文搭建了双脉冲实验平台,对4.5 kV、1.2 kA IGBT模块开关瞬态时的热敏感电参数进行了测量,并对每个参数是否适用在线结温提取以及预期成本进行了讨论。结果表明,大多数参数除温度外还强烈依赖于负载电流和母线电压,最合适的结温提取参数是准阈值电压和开通时集电极电流变化率,它们都可以通过IGBT的寄生电感来获取。     

计及磁饱和的同步发电机内电势幅值测量方法

在直接测量转子位置获取同步发电机内电势相位的基础上,给出了同步发电机内电势幅值的准确直接计算方法,该方法的准确性只依赖于机端电压、机端电流、发电机功角等电气测量结果的准确性,与同步发电机参数无关。同时,基于内电势幅值和相位的准确测量,给出了能够计及磁路饱和影响的同步发电机定子与转子间互感电抗和同步电抗的计算方法,并基于正态分布参数估计理论,给出电抗计算结果的置信区间和点估计值,实际算例表明,所述方法准确可靠。     

Design, fabrication and characterization of dual-channel real space transfer transistor

In this paper, using a δ-doping dual-channel structure and GaAs substrate, a real space transfer transistor (RSTT) is designed and fabricated successfully. It has the standard Λ-shaped negative resistance I–V characteristics as well as a level and smooth valley region that the conventional RSTT has. The negative resistance parameters can be varied by changing gate voltage (V _GS). For example, the PVCR varies from 2.1 to 10.6 while V _GS changes from 0.6 V to 1.0 V. The transconductance for I _P (ΔI _P/ΔV _GS) is 0.3 mS. The parameters of V _P, V _V and threshold gate voltage (V _T) for negative resistance characteristics arising are all smaller than the value reported in the literature. Therefore, this device is suitable for low dissipation power application. __________ Translated from Journal of Semiconductors, 2008, 29(1): 136–139 [译自: 半导体学报]     

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Current‐oriented operational amplifier (OpAmp) design has been common for its orderly current‐to‐speed tradeoff. However, for high‐precision or high‐linearity applications, increasing the current does not help much, as the supply voltage (V_DD) and intrinsic gain of the MOSFETs in ultra‐scaled CMOS technologies are very limited. This paper introduces voltage‐oriented circuit techniques to address such limitations. Specifically, a 2xV_DD‐enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V_DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV_DD RFC and FC counterparts, the proposed solution achieves 20‐dB higher DC gain (i.e. 72.8 dB) in open loop and 20‐dB lower IM3 (i.e., –76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1‐V General Purpose 65‐nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi‐stage OpAmps. Voltage‐conscious biasing and node‐voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high‐voltage device is necessary. Copyright © 2012 John Wiley & Sons, Ltd.     

Output characteristics model for an a‐Si ISFET pH sensor

A mathematical model for the calculation of the output characteristics of amorphous silicon hydrogenated (a‐Si:H) ion‐sensitive field‐effect transistors (ISFET) is developed, which depends on the integration of the conductivity channel versus gate voltage curve at fixed drain voltage. Single curve integration was changed to integration with many simple lines to obtain the I_D − V_D characteristics using computer programming. The results of this model were tested with those of experiments. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Inner Intrinsically Safe Criterion and Design Considerations of Buck Converter Based on Equivalent Inductance

To obtain the intrinsic safety criterion of the Inner-intrinsic-Safety-Buck-Converter (ISBC) based on equivalent-inductance to guide its optimal design, the Inductor Disconnected Discharge (IDD) behavior of ISBC is researched, and the Equivalent-Simple-Inductive-Circuit (ESIC) based on the equivalent inductance is defined. According to ESIC based on the equivalent-current and the energy equivalence, the expression of the equivalent inductance L_ei is derived. The effect of the inductance L, the capacitance C, the input voltage V_i and the load resistance R_L on L_ei is deeply studied, and it’s pointed out that L_ei increases with the increase of V_i, L, C, and R_L, respectively. According to the minimal ignition current curve of the Simple-Inductive-Circuit (SIC), the nonexplosive intrinsically safe criterion based on L_ei is proposed. Combining the proposed criterion, the output ripple voltage and the expression of L_ei, the design region of the capacitance and inductance of the Buck converter meeting the demands of both inner intrinsic safety and electric performance is obtained. The feasibility of the design method and the proposed criterion is proved by the simulation and experimental results.     

Synthesis of superconducting Bi2Sr2CaCu2O8+δ single crystals using alumina crucibles with different purities

A self‐flux method is the simplest technique for synthesizing Bi₂Sr₂CaCu₂O_8+δ (Bi‐2212) superconducting single crystals. However, the crystals are inevitably contaminated because of the Bi‐2212 stoichiometric melt reacting with the crucible material. In this paper, we investigate the nonsuperconducting subproduct that forms during heating in the self‐flux method for synthesizing Bi‐2212. This subproduct was identified as BiSr₂CaAl₃O₉ by X‐ray diffraction. Bi‐2212 crystal growth was performed using A1₂O₃ crucibles with three different purities (nominally 97, 99.7, and 99.9%). For both the 97 and 99.7% purity crucibles, the subproduct was observed in all five samples out of five, whereas for the 99.9% purity crucible, it was observed in only two samples out of five. Furthermore, the 99.9% purity crucible gave a much lower subproduct volume than the 97% purity crucible. The average superconducting critical temperature (T_c,zero) varied depending on the crucible purity; it was 89.6, 90.8, and 91.8 K for the 97, 99.7, and 99.9% purity crucibles, respectively. Finally, we fabricated Bi‐2212 stacked devices with intrinsic Josephson junctions (Bi‐2212 stack) using as‐grown crystals from the 97 and 99.9% purity crucibles. The Bi‐2212 stacks exhibited a highly hysteretic current–voltage characteristic even at liquid N₂ temperature and they had identical quality parameters for Josephson junctions (i.e., I_r/I_c and voltage jump V_j). We conclude that the subproduct formation has little effect on the electrical characteristics of a Josephson junction device at 77 K. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Noise immune dielectric modulated dual trench transparent gate engineered MOSFET as a label free biosensor: proposal and investigation

We propose and investigate a biosensor based on a transparent dielectric-modulated dual-trench gate-engineered metal–oxide–semiconductor field-effect transistor (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Various sensing parameters such as the I_ON/I_OFF ratio and the threshold voltage shift are evaluated as metrics to validate the proposed sensing device. Additionally, S_Vth (the V_th sensitivity) is also analyzed, considering both positively and negatively charged biomolecules. In addition, radiofrequency (RF) sensing parameters such as the transconductance gain and the cutoff frequency are taken into account to provide further insight into the sensitivity of the proposed device. Furthermore, the linearity, distortion, and noise immunity of the device are evaluated to confirm the overall performance of the biosensor at high (GHz) frequency. The results indicate that the proposed biosensor exhibits a S_Vth value of 0.68 for positively charged biomolecules at a very low drain bias of 0.2 V. The proposed device can thus be used as an alternative to conventional FET-based biosensors.

     

Electrical characteristics of high dielectric constant BCTZ thin films

Abstract

High dielectric constant Ba_0.96Ca_0.04Ti_0.84Zr_0.16O₃ (BCTZ) thin films were deposited on Pt/Ti/SiO₂/Si substrates by spin on metal-organic decomposition (MOD) technique. Undoped and 0.4% Mg-doped BCTZ thin films were annealed in the temperature range from 600 to 900 °C for 1 hour in oxygen environment. The crystal structure of BCTZ thin films was analyzed by X-ray diffraction. The electrical properties of BCTZ thin films were investigated by capacitance—voltage (C—V) characteristics. Also, the electrical properties of these films were compared in conjunction with 0.4% Mg doping effect of BCTZ thin films for possible high dielectric constant material applications.     

STATCOM using the new concept of an inverter system with controlled gradational voltage

This paper presents the STATCOM using the new concept of an inverter system which consists of three inverter units connected in series, and each inverter unit generates a different input voltage such as V_C, 2V_C, 4V_C. This inverter system can output a high‐quality voltage by a low‐frequency switching operation. Thus, it can combine low loss and high quality. In this paper, we show the technique to apply STATCOM which uses the inverter system, and examination results. © 2009 Wiley Periodicals, Inc. Electr Eng Jpn, 168(4): 58–65, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ).DOI 10.1002/eej.20823